KSZ9031MNX View Datasheet(PDF) - Micrel
Part Name
Description
Manufacturer
KSZ9031MNX Datasheet PDF : 77 Pages
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Micrel, Inc.
KSZ9031MNX
Pin Number
48
Pin Name
RX_CLK/
PHYAD2
49
CRS
50
MDC
51
MDIO
52
COL
53
INT_N/
PME_N2
54
DVDDL
55
CLK125_NDO/
LED_MODE
56
RESET_N
57
TX_CLK
58
LDO_O
59
AVDDL_PLL
60
XO
61
XI
62
NC
Type(1)
I/O
O
Ipu
Ipu/O
O
O
P
I/O
Ipu
O
O
P
O
I
-
Pin Function
GMII mode:
GMII RX_CLK (Receive Reference Clock) output
MII mode:
MII RX_CLK (Receive Reference Clock) output
Config mode:
The voltage on this pin is sampled and latched during the
power-up/reset process to determine the value of PHYAD[2].
See the “Strapping Options” section for details.
GMII mode:
GMII CRS (Carrier Sense) output
MII mode:
MII CRS (Carrier Sense) output
Management data clock input
This pin is the input reference clock for MDIO (pin 51).
Management data input/output
This pin is synchronous to MDC (pin 50) and requires an external pull-up resistor
to DVDDH (digital VDD) in a range from 1.0kΩ to 4.7kΩ.
GMII mode:
GMII COL (Collision Detected) output
MII mode:
MII COL (Collision Detected) output
Interrupt output: Programmable interrupt output, with register 1Bh as the Interrupt
Control/Status register, for programming the interrupt conditions
and reading the interrupt status. Register 1Fh, bit [14] sets
the interrupt output to active low (default) or active high.
PME_N output: Programmable PME_N output (pin option 2). When asserted
low, this pin signals that a WOL event has occurred.
For Interrupt (when active low) and PME functions, this pin requires an external
pull-up resistor to DVDDH (digital VDD_I/O) in a range from 1.0kΩ to 4.7kΩ.
1.2V digital VDD
125MHz clock output
This pin provides a 125MHz reference clock output option for use by the MAC.
Config mode:
The voltage on this pin is sampled during the power-up/reset
process to determine the value of LED_MODE. See the
“Strapping Options” section for details.
Chip reset (active low)
Hardware pin configurations are strapped-in (sampled and latched) at the de-
assertion (rising edge) of RESET_N. See the “Strapping Options” section for more
details.
MII mode:
MII TX_CLK (Transmit Reference Clock) output
On-chip 1.2V LDO controller output
This pin drives the input gate of a P-channel MOSFET to generate 1.2V for the
chip’s core voltages. If the system provides 1.2V and this pin is not used, it can be
left floating.
1.2V analog VDD for PLL
25MHz crystal feedback
This pin connects to one end of an external 25MHz crystal.
This pin is a no connect if an oscillator or other external (non-crystal) clock source
is used.
Crystal / Oscillator/ External Clock input
This pin connects to one end of an external 25MHz crystal or to the output of an
oscillator or other external (non-crystal) clock source.
25MHz ±50ppm tolerance
No connect
This pin is not bonded and can be connected to AVDDH power for footprint
compatibility with the Micrel KSZ9021GN Gigabit PHY.
October 2012
14
M9999-103112-1.0
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