KSZ9031MNX View Datasheet(PDF) - Micrel

Part Name

Description

Manufacturer

KSZ9031MNX

Gigabit Ethernet Transceiver with GMII/MII Support

Micrel 

Micrel, Inc.

KSZ9031MNX

List of Figures

Figure 1. KSZ9031MNX Block Diagram .............................................................................................................................. 17

Figure 2. KSZ9031MNX 1000Base-T Block Diagram – Single Channel ............................................................................. 19

Figure 3. Auto-Negotiation Flow Chart................................................................................................................................. 22

Figure 4. KSZ9031MNX GMII Interface ............................................................................................................................... 24

Figure 5. KSZ9031MNX MII Interface .................................................................................................................................. 26

Figure 6. Local (Digital) Loopback ....................................................................................................................................... 29

Figure 7. Remote (Analog) Loopback .................................................................................................................................. 30

Figure 8. LPI Mode (Refresh Transmissions and Quiet Periods) ........................................................................................ 32

Figure 9. LPI Transition – GMII (1000Mbps) Transmit ........................................................................................................ 33

Figure 10. LPI Transition – MII (100Mbps) Transmit ........................................................................................................... 33

Figure 11. LPI Transition – GMII (1000Mbps) Receive ....................................................................................................... 34

Figure 12. LPI Transition – MII (100Mbps) Receive ............................................................................................................ 34

Figure 13. GMII Transmit Timing – Data Input to PHY ........................................................................................................ 63

Figure 14. GMII Receive Timing – Data Input to MAC ........................................................................................................ 64

Figure 15. MII Transmit Timing – Data Input to PHY ........................................................................................................... 65

Figure 16. MII Receive Timing – Data Input to MAC ........................................................................................................... 66

Figure 17. Auto-Negotiation Fast Link Pulse (FLP) Timing ................................................................................................. 67

Figure 18. MDC/MDIO Timing.............................................................................................................................................. 68

Figure 19. Power-Up/Power-Down/Reset Timing ................................................................................................................ 69

Figure 20. Recommended Reset Circuit .............................................................................................................................. 70

Figure 21. Recommended Reset Circuit for Interfacing with CPU/FPGA Reset Output ..................................................... 70

Figure 22. Reference Circuits for LED Strapping Pins......................................................................................................... 71

Figure 23. 25MHz Crystal/Oscillator Reference Clock Connection ..................................................................................... 72

Figure 24. Typical Gigabit Magnetic Interface Circuit .......................................................................................................... 73

Figure 25. Recommended Land Pattern, 64-Pin (8mm x 8mm) QFN ................................................................................. 75

October 2012

7

M9999-103112-1.0

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