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KSZ9031MNX View Datasheet(PDF) - Microsemi Corporation

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Description
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KSZ9031MNX Datasheet PDF : 73 Pages
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KSZ9031MNX
The KSZ9031MNX combines GMII mode with MII mode to form GMII/MII mode to support data transfer at 10/100/
1000 Mbps. After power-up or reset, the KSZ9031MNX is configured to GMII/MII mode if the MODE[3:0] strap-in pins
are set to ‘0001’. See the Strapping Options - KSZ9031MNX section.
The KSZ9031MNX has the option to output a 125 MHz reference clock on CLK125_NDO (Pin 55). This clock provides
a lower-cost reference clock alternative for GMII/MII MACs that require a 125 MHz crystal or oscillator. The 125 MHz
clock output is enabled after power-up or reset if the CLK125_EN strap-in pin is pulled high.
The KSZ9031MNX provides a dedicated transmit clock input pin (GTX_CLK, Pin 32) for GMII mode, which is sourced
by the MAC for 1000 Mbps speed.
3.9.1 GMII SIGNAL DEFINITION
Table 3-3 describes the GMII signals. Refer to Clause 35 of the IEEE 802.3 Specification for more detailed information.
TABLE 3-3: GMII SIGNAL DEFINITION
GMII Signal Name
(per spec)
GMII Signal Name
(per KSZ9031MNX)
Pin Type (with
respect to PHY)
Pin Type (with
respect to MAC)
Description
GTX_CLK
TX_EN
TXD[7:0]
TX_ER
RX_CLK
RX_DV
RXD[7:0]
RX_ER
CRS
COL
GTX_CLK
TX_EN
TXD[7:0]
TX_ER
RX_CLK
RX_DV
RXD[7:0]
RX_ER
CRS
COL
Input
Input
Input
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Transmit Reference Clock
(125 MHz for 1000 Mbps)
Transmit Enable
Transmit Data[7:0]
Transmit Error
Receive Reference Clock
(125 MHz for 1000 Mbps)
Receive Data Valid
Receive Data[7:0]
Receive Error
Carrier Sense
Collision Detected
3.9.2 GMII SIGNAL DIAGRAM
The KSZ9031MNX GMII pin connections to the MAC are shown in Figure 3-4.
FIGURE 3-4:
KSZ9031MNX GMII INTERFACE
KSZ9031MNX
GTX _CLK
TX _EN
TXD [7:0]
TX _ER
GMII
ETHERNET MAC
GTX _CLK
TX _EN
TXD [7:0]
TX _ER
RX_CLK
RX _DV
RXD[7:0]
RX _ER
CRS
COL
RX_CLK
RX _DV
RXD[7:0]
RX _ER
CRS
COL
2016 Microchip Technology Inc.
DS00002096C-page 19

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