XRD8794AB View Datasheet(PDF) - Exar Corporation

Part Name

Description

Manufacturer

XRD8794AB

XRD8794AB Application Board

Exar Corporation 

XRD8794AB

Reference must be stable to

1 LSB > 50 ns from next clock edge Reference must be stable for tAP + 10 ns

after rising clock edge

Reference

Stable Time for Sample N

Stable Time for Sample N+2

External Clock

Aperture

50 ns

AIN Sample Window

Sample N

End of Sample N

Ladder Compare Window

(MSB Bank)

Ladder Compare Window

(LSB Bank)

Compare N

for MSBs

Data Out

N–3

Invalid

End of Sample N+2

Compare N

for LSBs

N–2

Valid

N–1

Invalid

N

Valid

Figure 6. Timing For The Dynamically Adjusted Reference Ladder

(Pixel-by-Pixel Adjustment)

SYSTEM OPERATION

Hence VREF(-) defines the offset and VREF(+) defines the

span.

Reference Inputs

With the reference op amps in circuit, the ADC’s reference

pins (VRB and VRT) are driven in an offset and range

mode:

VRB = VREF(-), VRT = VREF(-) + VREF(+)

AIN Input

If the DITHER input is left floating, then the input to the

ADC (ADCIN) is given by:

ADCIN = AIN

If JP1 is in, then the input to the ADC (ADCIN) is given by:

ADCIN = [1 + (R5 / (R3 + R2)) ] AIN

Rev. 1.00

8

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