XR16C2852IJ(2002) View Datasheet(PDF) - Exar Corporation

Part Name

Description

Manufacturer

XR16C2852IJ
(Rev.:2002)

3.3V AND 5V DUART WITH 128-BYTE FIFO

Exar Corporation 

XR16C2852

REV. 2.0.0

3.3V AND 5V DUART WITH 128-BYTE FIFO

FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE

Data

Byte

Transmit

Holding

Register

(THR)

THR Interrupt (ISR bit-1)

Enabled by IER bit-1

áç

16X

Clock

Transmit Shift Register (TSR)

M

L

S

S

B

B

TXNOFIFO1

2.11.3 Transmitter Operation in FIFO Mode

The host may fill the transmit FIFO with up to 128

bytes of transmit data. The THR empty flag (LSR bit-

5) is set whenever the FIFO is empty. The THR empty

flag can generate a transmit empty interrupt (ISR bit-

1) when the amount of data in the FIFO falls below its

programmed trigger level. The transmit empty inter-

rupt is enabled by IER bit-1. The TSR flag (LSR bit-6)

is set when TSR/FIFO becomes empty.

FIGURE 8. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE

T rans m it

Data Byte

Auto CTS Flow Control (CTS# pin)

Flow Control Characters

(Xoff1/2 and Xon1/2 Reg.

Auto Software Flow Control

T rans m it

FIFO

THR Interrupt (ISR bit-1) falls

below the programmed Trigger

Level and then when becomes

empty. FIFO is Enabled by FCR

bit-0=1

16X Clock

Transmit Data Shift Register

(TSR)

TXFIFO1

2.12 RECEIVER

The receiver section contains an 8-bit Receive Shift

Register (RSR) and 128 bytes of FIFO which includes

a byte-wide Receive Holding Register (RHR). The

RSR uses the 16X for timing. It verifies and validates

every bit on the incoming character in the middle of

each data bit. On the falling edge of a start or false

start bit, an internal receiver counter starts counting

at the 16X. After 8 clocks the start bit period should

be at the center of the start bit. At this time the start

bit is sampled and if it is still a logic 0 it is validated.

Evaluating the start bit in this manner prevents the re-

ceiver from assembling a false character. The rest of

the data bits and stop bits are sampled and validated

in this same manner to prevent false framing. If there

were any error(s), they are reported in the LSR regis-

ter bits 2-4. Upon unloading the receive data byte

from RHR, the receive FIFO pointer is bumped and

the error tags are immediately updated to reflect the

status of the data byte in RHR register. RHR can gen-

erate a receive data ready interrupt upon receiving a

character or delay until it reaches the FIFO trigger

level. Furthermore, data delivery to the host is guar-

anteed by a receive data ready time-out interrupt

when data is not received for 4 word lengths as de-

fined by LCR[1,0] plus 12 bits time. This is equivalent

to 3.7-4.6 character times. The RHR interrupt is en-

abled by IER bit-0.

11

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