KAD2710L-27Q68 View Datasheet(PDF) - Renesas Electronics
Part Name
Description
Manufacturer
KAD2710L-27Q68 Datasheet PDF : 17 Pages
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KAD2710L
This relationship shows the SNR that would be achieved if
clock jitter were the only non-ideal factor. In reality, achievable
SNR is limited by internal factors such as linearity, aperture
jitter and thermal noise. Internal aperture jitter is the
uncertainty in the sampling instant shown in Figure 1.
Any internal aperture jitter combines with the input clock jitter in
a root-sum-square fashion, since they are not statistically
correlated, and this determines the total jitter in the system.
The total jitter, combined with other noise sources, then
determines the achievable SNR.
Digital Outputs
Data is output on a parallel bus with LVDS-compatible drivers.
The output format (Binary or Two’s Complement) is selected
via the 2SC pin as shown in Table 3.
TABLE 3. 2SC PIN SETTINGS
2SC PIN
MODE
AVSS
Two’s Complement
AVDD (or unconnected)
Binary
Equivalent Circuits
AVDD3
INP
2pF
F 2
F 1
AVDD3
INN
2pF
F 2
F 1
Csamp
0.3pF
To
Charge
Pipeline
Csamp
0.3pF
To
Charge
Pipeline
AVDD2
CLKP
AVDD2
CLKN
AVDD2
To Clock
Generation
FIGURE 28. ANALOG INPUTS
OVDD
FIGURE 29. CLOCK INPUTS
DATA
DATA
DATA
OVDD
OVDD
D[9:0]P,
ORP
DATA
D[9:0]N,
ORN
FIGURE 30. LVDS OUTPUTS
FN6818 Rev 0.00
December 5, 2008
Page 14 of 17
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