HMP8154 View Datasheet(PDF) - Renesas Electronics
Part Name
Description
Manufacturer
HMP8154 Datasheet PDF : 34 Pages
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HMP8154, HMP8156A
CLK2
P8-P15
OL0-OL2,
M1, M0
BLANK
(INPUT)
BLANK
(OUTPUT)
Cb 0
Y0
Cr 0
Y1
Cb 2
Y2
PIXEL 0
PIXEL 1
PIXEL 2
YN
PIXEL N
FIGURE 1. PIXEL AND OVERLAY INPUT TIMING - NORMAL 8-BIT YCBCR
CLK2
CLK
P8-P15
Cb 0
Y0
Cr 0
Y1
Cb 2
Y2
YN
OL0-OL2,
M1, M0
BLANK
(INPUT)
BLANK
(OUTPUT)
PIXEL 0
PIXEL 1
PIXEL 2
PIXEL N
FIGURE 2. PIXEL AND OVERLAY INPUT TIMING - 8-BIT YCBCR WITH 2X UPSCALING
Normal 16-Bit YCbCr, 16-Bit RGB, 24-Bit RGB
Formats
When 16-bit YCbCr, 16-bit RGB data, or 24-bit RGB format
is selected without 2X upscaling or flicker filtering, the pixel
data is latched on the rising edge of CLK2 while CLK is low.
Overlay data is also latched on the rising edge of CLK2 while
CLK is low. The pixel and overlay input timing is shown in
Figures 3 - 5.
As inputs, BLANK, HSYNC, and VSYNC are latched on the
rising edge of CLK2 while CLK is low. As outputs, HSYNC,
VSYNC, and BLANK are output following the rising edge of
CLK2 while CLK is high. In these modes of operation, CLK is
one-half the CLK2 frequency.
FN4343 Rev.5.00
August 20, 2009
Page 7 of 34
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