CDB53L32A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CDB53L32A Datasheet PDF : 40 Pages
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CS53L32A
SWITCHING CHARACTERISTICS (TA = -10 to 70° C; VA = 1.7 V - 3.6 V; Inputs: Logic 0 = GND,
Logic 1 = VL, CL = 20 pF)
Parameters
Input Sample Rate
Base Rate Mode
High Rate Mode
MCLK Pulse Width High
MCLK/LRCK = 1024
MCLK Pulse Width Low
MCLK/LRCK = 1024
MCLK Pulse Width High
MCLK/LRCK = 768
MCLK Pulse Width Low
MCLK/LRCK = 768
MCLK Pulse Width High
MCLK/LRCK = 512
MCLK Pulse Width Low
MCLK/LRCK = 512
MCLK Pulse Width High MCLK / LRCK = 384 or 192
MCLK Pulse Width Low MCLK / LRCK = 384 or 192
MCLK Pulse Width High MCLK / LRCK = 256 or 128
MCLK Pulse Width Low MCLK / LRCK = 256 or 128
Master Mode
SCLK Falling to LRCK Edge
SCLK Falling to SDOUT Valid
SCLK Duty Cycle
Slave Mode
LRCK Duty Cycle
Notes 8, 9
Rise Time of Both LRCK and SCLK
Fall Time of Both LRCK and SCLK
SCLK Period
Base Rate Mode
Symbol
Fs
Fs
tslrd
tsdo
tr
tf
tsclkw
High Rate Mode tsclkw
Min
2
50
8
8
10
10
15
15
21
21
31
31
-20
0
40
-
-
-
(---1---2---8-1---)---F----s-
--------1----------
(64 )Fs
Typ Max Units
-
50
kHz
-
100
kHz
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
20
ns
-
20
ns
50
60
%
50
-
%
-
10
ns
-
10
ns
-
-
ns
-
-
ns
SCLK Falling to LRCK Edge
SCLK Falling to SDOUT Valid
tslrd
Base Rate Mode tdss
High Rate Mode tdss
-20
-
20
ns
-
-
1
ns
(512)Fs
-
-
1
ns
(256)Fs
NOTE: When operating the CS53L32A Revision C in Slave Mode, Base Rate Mode, certain timing requirements
must be met in addition to those specified above. The required timing relationship between the MCLK and LRCK
is shown in Figures 3. An MCLK rising edge cannot lead an LRCK transition by 6ns to 10ns.
8. There must be exactly 32, 48, 64, or 128 SCLK periods per LRCK transition.
9. Slave Mode operation requires an exact 50% duty cycle. Otherwise the CS53L32A will produce
erroneous data.
10
DS513F1
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