PI6C3Q993-5IQ View Datasheet(PDF) - Pericom Semiconductor

Part Name

Description

Manufacturer

PI6C3Q993-5IQ

3.3V Programmable Skew PLL Clock Driver SuperClock®

Pericom Semiconductor 

PI6C3Q991, PI6C3Q993

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Programmable Skew

Output skew with respect to the REF input is adjustable to compen-

sate for PCB trace delays, backplane propagation delays or to

accommodate requirements for special timing relationships between

clocked components. Skew is selectable as a multiple of a time unit

tU which is of the order of a nanosecond (see Table 2). There are 9

skew configurations available for each output pair. These configu-

rations are choosen by the nF1:0 control pins. In order to minimize

the number of control pins, 3-level inputs (HIGH-MID-LOW) are

used, they are intended for but not restricted to hard-wiring. Undriven

3-level inputs default to the MID level. Where programmable skew

is not a requirement, the control pins can be left open for the zero skew

default setting. The Skew Selection Table (Table 3) shows how to

select specific skew taps by using the nF1:0 control pins.

External Feedback

By providing external feedback, the PI6C3Q99X family gives users

flexibility with regard to skew adjustment. The FB signal is compared

with the input REF signal at the phase detector in order to drive the

VCO. Phase differences cause the VCO of the PLL to adjust upwards

or downwards accordingly. An internal loop filter moderates the

response of the VCO to the phase detector. The loop filter transfer

function has been chosen to provide minimal jitter (or frequency

variation) while still providing accurate responses to input fre-

quency changes.

Table 2. PLL Programmable Skew Range and Resolution Table

FS = LOW FS = MID FS = HIGH Comments

Timing unit calculation (tU)

VCO frequency range (FNOM)(1,2)

Skew adjustment range(3) Max.

adjustment

1/(44xFNOM) 1/(26xFNOM) 1/(16xFNOM)

15 to 35 MHz 25 to 60 MHz 40 to 85 MHz

±9.09ns

±49°

±14%

±9.23ns

±83°

±23%

±9.38ns

±135°

±37%

ns Phase degrees

% of cycle time

Example 1, FNOM = 15 MHz

Example 2, FNOM = 25 MHz

Example 3, FNOM = 30 MHz

Example 4, FNOM = 40 MHz

Example 5, FNOM = 50 MHz

Example 6, FNOM = 80 MHz

tU = 1.52ns

tU = 0.91ns

tU = 0.76ns

tU = 1.54ns

tU = 1.28ns

tU = 0.96ns

tU = 0.77ns

tU = 1.56ns

tU = 1.25ns

tU = 0.78ns

Notes:

1. The device may be operated outside recommended frequency ranges without damage, but functional

operation is not guaranteed. Selecting the appropriate FS value based on input frequency range allows the

PLL to operate in its ‘sweet spot’ where jitter is lowest.

2. The level to be set on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator.

The VCO frequency always appears at 1Q1:0, 2Q1:0, and the higher outputs when they are operated in their

undivided modes. The frequency appearing at the REF and FB inputs will be the same as the VCO when the

output connected to FB is undivided. The frequency of the REF and FB inputs will be 1/2 or 1/4 the VCO

frequency when the part is configured for a frequency multiplication by using a divided output as the FB input.

3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used

for feedback, then adjustment range will be greater. For example if a 4tU skewed output is used for feedback,

all other outputs will be skewed –4tU in addition to whatever skew value is programmed for those outputs.

‘Max adjustment’ range applies to output pairs 3 and 4 where ±6 tU skew adjustment is possible and at the

lowest FNOM value.

3

PS8449A 10/09/00

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