AD708 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD708 Datasheet PDF : 8 Pages
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AD708
As configured, the circuit only requires a gain resistor, RG, of
suitable accuracy and a stable, accurate voltage reference. The
transfer function is:
VO = VREF [∆R/(R+∆R)][RG/R]
and the only significant errors due to the AD708S are:
VOSout = (VOSmatch)(2RG/R) = 30 mV
VOSout(T) = (VOSdrift)(2RG/R) = 0.3 mV/°C
To achieve high accuracy, the resistor RG should be 0.1% or
better and have a low drift coefficient.
Figure 29. Bridge Signal Conditioning Circuit
Figure 31. Absolute Value Circuit Performance
(Input Signal = 0.05 Hz)
SELECTION OF PASSIVE COMPONENTS
To takc full advantagc of thc high precision and low drift
characteristics of the AD708, high quality passive components
must be used. Discrete resistors and resistor networks with
temperature coefficients of less than 10 ppm/°C are available
from Vishay, Caddock, PRP and others.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
TO-99 (H) Package
Figure 30. Precision Absolute Value Circuit
PRECISION ABSOLUTE VALUE CIRCUIT
The AD708 is ideally suited to the precision absolute value
circuit shown in Figure 30. The low offset voltage match of the
AD708 enables this circuit to accurately resolve the input signal.
In addition, the tight offset voltage drift match maintains the
resolution of the circuit over the full military temperature range.
The AD708’s high dc open loop gain and exceptional gain
linearity allows the circuit to perform well at both large and
small signal levels.
In this circuit, the only significant dc errors are due to the offset
voltage of the two ampliliers, the input offset current match of
the amplifiers, and the mismatch of the resistors. Errors associ-
ated with the AD708S contribute less than 0.001% error over
–55°C to +125°C.
Maximum error at 25°C
30
µV
+ (10 kΩ)
10 V
(1nA)
=
40
µV /10 V
=
4
ppm
Maximum
error at +125°C or –55°C
50
µV
+
(2 nA)
10 V
(10
kΩ)
=
7
ppm
@
+125°C
Figure 31 shows VOUT vs. VIN for this circuit with a ± 3 mV
input signal at 0.05 Hz. Note that the circuit exhibits very low
offset at the zero crossing. This circuit can also produce VOUT =
–|VIN| by reversing the polarity of the two diodes.
–8–
Cerdip (Q) Package
Mini-DIP (N) Package
REV. B
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