LC72711LW View Datasheet(PDF) - SANYO -> Panasonic
Part Name
Description
Manufacturer
LC72711LW Datasheet PDF : 26 Pages
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LC72711W, 72711LW
Layer 4 CRC Register
Address Register R/W Initial value
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
06H
CRC4
W
00H
(LSB)
This is the data group write register used for the layer 4 CRC check. It is used only when the parallel interface is used.
Applications should specify the dedicated CCB address when using the serial interface.
Status Register
Address Register R/W Initial value
BIT7
BIT6
01H
STAT
R
-
VH
BLK
BIT5
FRM
BIT4
ERR
BIT3
PRI
BIT2
HEAD
BIT1
CRC4
BIT0
RTIB
• VH
0: Indicates data for which only horizontal correction was performed.
1: Indicates data for which after horizontal correction, vertical and then second horizontal correction were performed
as well.
Packet data with an RTIB flag is output with VH set to 0.
• BLK
0: Indicates data that was received with block synchronization unsynchronized.
1: Indicates data that was received with block synchronization synchronized.
• FRM
0: Indicates data that was received with frame synchronization unsynchronized.
1: Indicates data that was received with frame synchronization synchronized.
• ERR
0: Indicates data for which error correction completed and no errors were detected in the level 2 CRC check.
1: Indicates data for which error correction was not possible or for which errors were detected in the level 2 CRC
check.
• PRI
0: Indicates data that was inferred to be data block data by the frame synchronization circuit.
1: Indicates data that was inferred to be parity block data by the frame synchronization circuit.
Packet data with an RTIB flag is output with PRI set to 0.
• HEAD
0:
1: Indicates data that was inferred to be in the frame head block by the frame synchronization circuit.
This flag is valid only when VH is 0.
• CRC4
0: Indicates that the layer 4 CRC detection circuit division registers were not all zeros.
1: Indicates that the layer 4 CRC detection circuit division registers were all zeros, i.e. that there were no errors.
The result at the point immediately prior to register readout is loaded into this flag.
• RTIB
0:
1: Indicates the data is a real-time information block. (This bit is valid only in method A’.)
This bit is fixed at 0 during method A and method B reception.
Block Number Register
Address Register R/W Initial value
02H BLNO
R
-
BIT7
BLN7
BIT6
BLN6
BIT5
BLN5
BIT4
BLN4
BIT3
BLN3
BIT2
BLN2
BIT1
BLN1
BIT0
BLN0
Indicates the block number or the parity block number of the output data.
A single frame consists of data blocks numbered 0 to 189 and parity blocks numbered 0 to 81. Output following
vertical correction does not include parity block data.
The value of the block number register is undefined if VEC_HALT (bit 2 in control register 1) is set to 1.
No.6167-11/26
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