BR9080AF-W View Datasheet(PDF) - ROHM Semiconductor
Part Name
Description
Manufacturer
BR9080AF-W Datasheet PDF : 13 Pages
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Memory ICs
BR9080AF-W / BR9080ARFV-W / BR9080ARFVM-W /
BR9016AF-W / BR9016ARFV-W / BR9016ARFVM-W
(3) Read cycle
BR9080AF-W / ARFV-W / ARFVM-W
H
SK
1
4
L
H
CS
L
H
DI
L
DO
1 010 1
HIGH-Z
H
R/B
WC
High or LOW
8
0 0 A0 A1
16
32
48
tCS
A7 A8
STANDBY
HIGH-Z
D0
D15 D0
D15
tOH
Read Data (n) Read Data (n+1)
Fig.4 BR9080AF-W / ARFV-W / ARFVM-W
BR9016 AF-W / ARFV-W / ARFVM-W
H
SK
1
4
8
L
H
CS
L
H
DI
L
DO
1 0 1 0 1 0 A0 A1 A2
HIGH-Z
H
R/B
WC
High or LOW
16
32
48
tCS
A8 A9
STANDBY
HIGH-Z
D0
D15 D0
D15
tOH
Read Data (n) Read Data (n+1)
Fig.5 BR9016AF-W / ARFV-W / ARFVM-W
1) After the fall of the 16th clock pulse, 16-bit data is output from the DO pin in synchronization with the falling edge of the
SK signal.
(DO output changes at a time lag of tPD0, tPD1 because of internal circuit delay following the falling edge of the SK signal.
During the tPD0 and tPD1 timing, the tPD time should be assured before data is read, to avoid the previous data being lost.
See the synchronized data input / output timing chart in Fig.2.)
2) The data stored in the next address is clocked out of the device on the falling edge of 32nd clock. The data stored in
the upper address every 16 clocks is output sequentially by the continual SK input. Also the read operation is reset by
CS High.
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