IDT74FCT32932-100PA View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
Manufacturer
IDT74FCT32932-100PA Datasheet PDF : 9 Pages
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IDT74FCT3932-100, IDT74FCT32932-100
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUIT
VCC
VIN
Pulse
Generator
D.U.T.
RT
VOUT
COMMERCIAL TEMPERATURE RANGES
ENABLE/DISABLE TEST CIRCUIT
VCC
VIN
Pulse
Generator
D.U.T.
CL
RT
VOUT
500Ω
6.0V
Open
GND
CL
500Ω
3267 drw 05
PROPAGATION DELAY, OUTPUT SKEW
3267 drw 06
REF_IN
INPUT
tPD
Q_FB
Qxx
Qyy
tSKEWr
tSKEWr
tSKEWall
Qzz
tSKEWr
tSKEWf
tSKEWf
tSKEWf
3V
1.5V
0V
VOH
1.5V
VOL
VOH
1.5V
VOL
VOH
1.5V
VOL
VOH
1.5V
VOL
3267 drw 07
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
3V
CONTROL
INPUT
t PZL
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
t PZH
OUTPUT SWITCH
NORMALLY OPEN
HIGH
3.5V
1.5V
1.5V
0V
1.5V
t PLZ
0V
3.5V
t PHZ
0.3V V OL
0.3V V OH
0V
NOTES:
3267 drw 08
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: tF ≤ 2.5ns; tR ≤ 2.5ns
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
6V
Enable Low
Disable High
Enable High
GND
All Other tests
Open
DEFINITIONS:
3267 lnk 14
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
9.9
8
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