M2V56S20AKT-5 View Datasheet(PDF) - MITSUBISHI ELECTRIC

Part Name

Description

Manufacturer

M2V56S20AKT-5

256M Synchronous DRAM

MITSUBISHI ELECTRIC  

SDRAM (Rev.1.31)

Single Data Rate

Apr. '02

PIN FUNCTION

CLK

Input

MITSUBISHI LSIs

M2V56S20/ 30/ 40 ATP

M2V56S20/ 30/ 40 AKT

256M Synchronous DRAM

Master Clock: All other inputs are referenced to the rising edge of CLK.

CKE

Input

/CS

/RAS, /CAS, /WE

Input

Input

Clock Enable: CKE controls internal clock. When CKE is low, internal

clock for the following cycle is ceased. CKE is also used to select auto

/ self refresh. After self refresh mode is started, CKE becomes

asynchronous input. Self refresh is maintained as long as CKE is low.

Chip Select: When /CS is high, any command are masked except

CLK, CKE and DQM

Combination of /RAS, /CAS, /WE defines basic commands.

A0-12

BA0,1

DQ0-15

Input

A0-12 specify the Row / Column Address in conjunction with BA0,1.

The Row Address is specified by A0-12. The Column Address is

specified by A0-9,11. A10 is also used to indicate precharge option.

When A10 is high at a read / write command, an auto precharge is

performed. When A10 is high at a precharge command, all banks are

precharged.

Input

Bank Address: BA0,1 specifies one of four banks to which a command

is applied. BA0,1 must be set with ACT, PRE, READ, WRITE

commands.

Input / Output Data In and Data out are referenced to the rising edge of CLK.

DQM

DQMU/L

Input

Din Mask / Output Disable: When DQMU/L is high in burst write, Din for

the current cycle is masked. When DQMU/L is high in burst read, Dout

is disabled at the next but one cycle.

Vdd, Vss

Power Supply Power Supply for the memory array and peripheral circuitry.

VddQ, VssQ Power Supply VddQ and VssQ are supplied to the Output Buffers only.

MITSUBISHI ELECTRIC

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