BT865A View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

BT865A

YCrCb to NTSC/PAL Digital Video Encoder

Unspecified 

CIRCUIT DESCRIPTION

HSYNC* Timing

Bt864A/865A

YCrCb to NTSC/PAL Digital Video Encoder

HSYNC* Timing

Master Mode

There are two HSYNC* timing modes in master mode; default mode and variable

HSYNC* timing mode. The variable HSYNC* timing mode is enabled by setting

ADJHSYNC high. This mode allows the user to specify the placement of the fall-

ing and rising edges of HSYNC* by using the HSYNCF and HSYNCR registers,

respectively. The values of registers HSYNCF and HSYNCR correspond to the

pixel count of the internal pixel counter (see Figure 3). HSYNCF and HSYNCR

cannot be zero and cannot be equal. Values must also be less than or equal to the to-

tal horizontal resolution given in Table 2. If the internal pixel counter resets before

the rising edge occurs, the part will not automatically reset, but will wait until the

pixel counter reaches the specified HSYNCR value. The placement of the analog

horizontal sync pulse is fixed relative to the internal pixel counter, therefore when

the rising and falling edges of HSYNC* are moved, the pipeline delay between the

HSYNC* pulse and the analog horizontal sync pulse is altered. In this mode, the

pipeline delay from HSYNC* to analog sync out is 40–(2*HSYNCF) if SYNCD-

LY = 0, and 41–(2*HSYNCF) if SYNCDLY = 1. In the default HSYNC* timing

mode, the placement of the edges of the HSYNC* pulse are fixed, with the excep-

tion of the one clock delay available through the register SYNCDLY. In this mode,

the pipeline delay from HSYNC* to analog sync out is 40 clocks if SYNCDLY =

0, and 41 clocks if SYNCDLY = 1. In the default mode, the delay from internal

horizontal pixel counter reset to the falling edge of HSYNC* is 2 clocks.

6

L865A_A unreleased

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