BT864AKPF View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

BT864AKPF

YCrCb to NTSC/PAL Digital Video Encoder

Unspecified 

CIRCUIT

DESCRIPTION

Pin Descriptions

Pin names, input/output assignments, numbers, and descriptions are listed in

Table 1. Figure 1 illustrates the Bt864A/865A pinout diagram, and Figure 2 details

the block diagram.

Table 1. Pin Assignments (1 of 3)

Pin Name

I/O

Pin #

Description

CLK

RESET*

BLANK*

VSYNC*

HSYNC*

P[7:0]

Y[7:0]

TTXDAT

TTXREQ

I 43

I 47

I 48

I/O 49

I/O 50

I 35–28

I 25, 24, 21–16

I 27

O 38

2x pixel clock input (TTL compatible).

Reset control input (TTL compatible). A logical zero disables and resets

video timing (horizontal, vertical, subcarrier counters to the start of

VSYNC of first field) and resets the I2C interface (but does not reset I2C

registers). RESET* must be a logical one for normal operation.

Composite blanking control input (TTL compatible). BLANK* is regis-

tered on the rising edge of CLK. The P[7:0] and Y[7:0] inputs are ignored

while BLANK* is a logical zero.

Vertical sync input/output (TTL compatible). As an output (master mode

operation), VSYNC* is output following the rising edge of CLK. As an

input (slave mode operation), VSYNC* is registered on the rising edge of

CLK.

Horizontal sync input/output (TTL compatible). As an output (master

mode operation), HSYNC* is output following the rising edge of CLK. As

an input (slave mode operation), HSYNC* is registered on the rising

edge of CLK.

YCrCb pixel inputs (TTL compatible) in 8-bit YCrCb mode. CrCb pixel

inputs (TTL compatible) in 16-bit YCrCb mode. A higher index corre-

sponds to a greater bit significance.

Y pixel inputs (TTL compatible) in 16-bit YCrCb mode. Y[7] enables

internal color bars when operating in 8-bit YCrCb mode. A higher index

corresponds to a greater bit significance.(1)

Teletext bit stream input (TTL compatible).(1)

Teletext request output (TTL compatible).

L865A_A unreleased

1

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