CXD2720Q View Datasheet(PDF) - Sony Semiconductor
Part Name
Description
Manufacturer
CXD2720Q Datasheet PDF : 40 Pages
| |||
CXD2720Q
(4) Details of Communication Methods
The definitions of signal timing required for control from the microcomputer are given below.
(4)-1. Write
First, address section data and mode section data are sent from the microcomputer, synchronized to SCK, to
the RVDT pin.
The address section data is 8 bits both for the coefficient RAM and setup register, and the setup register
transmits optional data for 1 word length. Address section data is sent with LSB first.
Mode section data is fixed at 8 bits regardless of content.
The phase relationship between SCK and RV data (data applied to the RVDT pin) has the following restrictions:
• RV data must be verified before SCK rise (tDS ≥ 20ns).
• RV data must be held for 1t + 20ns or more after SCK rise (tDH).
SCK itself has the following restrictions:
• SCK Low level must be 1t+ 20ns or more (tSWL).
• SCK High level must also be 1t + 20ns or more (tSWH).
After raising SCK which corresponds to mode section final data, XLAT is raised (tSLP ≥ 20ns). XLAT Low level
width must be maintained at 1t + 20ns or more (tLWL). Further, fall timing restrictions are:
• for the preceding transmission, if REDY falls due to SCK, as for write, 3t + 20ns or more is required. (tSLD)
• for the preceding transmission, if REDY falls due to XLAT, as for read, 20ns or more is required. (tLDR)
Further, if preceding transmissions have been performed and REDY = Low, it is necessary to wait for REDY =
High to raise XLAT.
The procedure until this point is the same for write and read.
RVDT
SCK
XLAT
REDY
TRDT
A0
tDS
tSWL
tSLD or tLWH
tLDR
High-Z
A7 M0
tDH
tSWH
D0/SQ00
D15/SQ23
M7
SQ00
SQ23
tSLP
tLWL
tRLP
tLSD
tSLD
tSBD
A0
tSS
tBSP
M7
tSLP
tLDR
tRLP
Figure 6-2. Write Timing
– 21 –
Share Link: 