7C1325-100(2000) View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
7C1325-100 Datasheet PDF : 16 Pages
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CY7C1325
Pin Descriptions
Pin Number Name
I/O
Description
85
ADSC
Input-
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted
Synchronous LOW, A[17:0] is captured in the address registers. A[1:0] are also loaded into the burst
counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
84
36, 37
ADSP
A[1:0]
Input-
Synchronous
Input-
Synchronous
Address Strobe from Processor, sampled on the rising edge of CLK. When asserted
LOW, A[17:0] is captured in the address registers. A[1:0] are also loaded into the burst
counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP
is ignored when CE1 is deasserted HIGH.
A1, A0 address inputs, These inputs feed the on-chip burst counter as the LSBs as
well as being used to access a particular memory location in the memory array.
50–44,
80–82, 99,
100, 32–35
A[17:2]
Input-
Address Inputs used in conjunction with A[1:0] to select one of the 256K address
Synchronous locations. Sampled at the rising edge of the CLK, if CE1, CE2, and CE3 are sampled
active, and ADSP or ADSC is active LOW.
94, 93
83
BWS[1:0]
ADV
Input-
Synchronous
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes.
Sampled on the rising edge. BWS0 controls DQ[7:0] and DP0, BWS1 controls DQ[15:8]
and DP1. See Write Cycle Descriptions table for further details.
Advance input used to advance the on-chip address counter. When LOW the internal
burst counter is advanced in a burst sequence. The burst sequence is selected using
the MODE input.
87
BWE
Input-
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal
Synchronous must be asserted LOW to conduct a byte write.
88
GW
Input-
Global Write Input, active LOW. Sampled on the rising edge of CLK. This signal is
Synchronous used to conduct a global write, independent of the state of BWE and BWS[1:0]. Global
writes override byte writes.
89
CLK
Input-Clock Clock input. Used to capture all synchronous inputs to the device.
98
CE1
Input-
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE2 and CE3 to select/deselect the device. CE1 gates ADSP.
97
CE2
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE1 and CE3 to select/deselect the device.
92
CE3
Input-
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE1 and CE2 to select/deselect the device.
86
OE
Input-
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O
Asynchronous pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins
are three-stated, and act as input data pins.
64
ZZ
Input-
Snooze Input. Active HIGH asynchronous. When HIGH, the device enters a low-pow-
Asynchronous er standby mode in which all other inputs are ignored, but the data in the memory
array is maintained. Leaving ZZ floating or NC will default the device into an active
state. ZZ has an internal pull down.
31
MODE
-
Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved
burst order. Pulled LOW selects the linear burst order. When left floating or NC,
defaults to interleaved burst order. Mode pin has an internal pull up.
23, 22, 19,
18, 13, 12, 9,
8, 73, 72, 69,
68, 63, 62,
59, 58
DQ[15:0]
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in
the memory location specified by A[17:0] during the previous clock rise of the read
cycle. The direction of the pins is controlled by OE in conjunction with the internal
control logic. When OE is asserted LOW, the pins behave as outputs. When HIGH,
DQ[15:0] and DP[1:0] are placed in a three-state condition. The outputs are automat-
ically three-stated when a WRITE cycle is detected.
74, 24
DP[1:0]
I/O-
Bidirectional Data Parity lines. These behave identical to DQ[15:0] described above.
Synchronous These signals can be used as parity bits for bytes 0 and 1 respectively.
15, 41, 65, VDD
91
Power Supply Power supply inputs to the core of the device. Should be connected to 3.3V power
supply.
3
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