7C1325-100 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
7C1325-100 Datasheet PDF : 13 Pages
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ADVANCED INFORMATION
Timing Diagrams (continued)
ZZ Mode Timing [14,15]
CLK
ADSP
ADSC
CE1
CE2
CE3
HIGH
LOW
HIGH
ZZ
ICC
I/Os
tZZS
ICC(active)
Three-state
ICCZZ
CY7C1325
tZZREC
Notes:
14. Device must be deselected when entering ZZ mode. See Cycle description for all possible signal conditions to deselect the device.
15. I/Os are in three-state when exiting ZZ sleep mode.
© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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