EL4585 View Datasheet(PDF) - Renesas Electronics

Part Name

Description

Manufacturer

EL4585

Horizontal Genlock, 8FSC

Renesas Electronics 

EL4585

FIGURE 10. COLPITTS OSCILLATOR

C1 is to adjust the center frequency, C2 DC isolates the

control from the oscillator, and V1 is the primary control

device. C2 should be much larger than CV so that V1 has

maximum modulation capability. The frequency of oscillation

is given by Equation 4:

F = -----------1-----------

2 LCT

CT = ---C----1----C----2-------+----C----C-1---1C----C-2---VC-----v---+-------C----1----C----V-----

(EQ. 4)

Choosing Loop Filter Components

The PLL, VCO, and loop filter can be described as:

Where:

Kd = phase detector gain in A/rad

F(s) = loop filter impedance in V/A

KVCO = VCO gain in rad/s/V

N = Total internal or external divisor (see 3 below)

It can be shown that for the loop filter shown in Equation 5:

C3 = K-----d--N-K----V----n2C----O--- C4 = C-1---0-3- R3 = K---2--d--N-K----V----C---n-O---

(EQ. 5)

Where n = loop filter bandwidth, and  = loop filter damping

factor.

1. Kd = 300µA/2rad = 4.77e-5A/rad for the EL4585.

2. The loop bandwidth should be about HSYNC

frequency/20, and the damping ratio should be 1 for

optimum performance. For our example,

n = 15.734kHz/20=787 Hz5000 rad/S.

3. N = 910x2 = 1820 from Table 1.

N = F---F-H--V---s-C--y---On---c- = 1---2-5--8-.--7-.-6-3---34---6-2---M6----k- = 1820 = 910x2

(EQ. 6)

4. KVCO represents how much the VCO frequency changes

for each volt applied at the control pin. It is assumed (but

FN7175 Rev 4.00

September 3, 2009

probably is not) linear about the lock point (2.5V). Its

value depends on the VCO configuration and the varactor

transfer function CV = F(VC), where VC is the reverse

bias control voltage, and CV is varactor capacitance.

Since F(VC) is nonlinear, it is probably best to build the

VCO and measure KVCO about 2.5V. The results of one

such measurement are shown below. The slope of the

curve is determined by linear regression techniques and

equals KVCO. For our example, KVCO = 9.06 Mrad/s/V.

FIGURE 11. FOSC vs VC, LC VCO

5. Now we can solve for C3, C4, and R3 in Equation 7:

C3 = K-----d--N-K----V----n2C----O--- = ---4---.--7--1-7--8--e--2---–0----5-----5---0-9--0-.--0-0--6----2e----6---- = 0.01F

C4 = -C1---0-3- = 0.001F

(EQ. 7)

R3 = K---2--d--N-K----V----C---2-O--- = ---42---.--7---7-1---8e---2--–--0--5------1---9---.--0-5--6-0---e-0---06---- = 42.1k

We choose R3 = 43k for convenience.

6. Notice R2 has little effect on the loop filter design. R2

should be large, around 100k, and can be adjusted to

compensate for any static phase error T at lock, but if

made too large, will slow loop response. If R2 is made

smaller, T (see “Timing Diagrams” on page 5) increases,

and if R2 increases, T decreases. For LDET to be low at

lock, |T| < 50ns. C4 is used mainly to attenuate high

frequency noise from the charge pump. The effect these

components have on-time to lock is illustrated in

Figure 12.

Lock Time

Let T = R3C3. As T increases, damping increases, but so

does lock time. Decreasing T decreases damping and

speeds up loop response, but increases overshoot and thus

increases the number of hunting oscillations before lock.

Critical damping (=1) occurs at minimum lock time.

Because decreased damping also decreases loop stability, it

is sometimes desirable to design slightly overdamped (>1),

trading lock time for increased stability.

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