EL4584 View Datasheet(PDF) - Renesas Electronics
Part Name
Description
Manufacturer
EL4584 Datasheet PDF : 15 Pages
| |||
EL4584
Timing Diagrams
200
FALLING EDGE OF HSYNC +
200ns LOCKS TO RISING EDGE
OF EXT DIV SIGNAL.
FIGURE 1. PLL LOCKED CONDITION (PHASE ERROR = 0)
200
E = (ttH) 360°
tH = HSYNC PERIOD
t = PHASE ERROR PERIOD
FIGURE 2. OUT OF LOCK CONDITION
FN7174 Rev 3.00
May 9, 2008
FIGURE 3. TEST CIRCUIT 1
Page 5 of 15
Share Link: 