Required Specifications and Test Diagrams (Continued)
Figure 9. LVTTL Output Propagation Delay and Transition Time Test Circuit
Notes:
17. A: ZO=50 and CT=15 pF distributed.
18. RL=100 and RS=950
Figure 10. LVDS Input to LVTTL Output Propagation Delay and Transition Time Waveforms
© 2003 Fairchild Semiconductor Corporation
FIN1049 • Rev. 1.0.3
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