Required Specifications and Test Diagrams (Continued)
Figure 11. LVTTL Output Enable / Disable Test Circuit
Notes:
19. A: ZO=50 and CT=15 pF distributed.
20. RL=100 , R1=1000 , and RS=950
Figure 12. LVTTL Output Enable / Disable Timing Waveforms
© 2003 Fairchild Semiconductor Corporation
FIN1049 • Rev. 1.0.3
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