C8051F520 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F520

8/4/2 kB ISP Flash MCU Family

Silicon Laboratories 

C8051F52x/F53x

List of Figures

Figure 1.1. C8051F53xA/F53x-C Block Diagram .................................................... 16

Figure 1.2. C8051F52xA/F52x-C Block Diagram .................................................... 16

Figure 1.3. C8051F53x Block Diagram (Silicon Revision A) ................................... 17

Figure 1.4. C8051F52x Block Diagram (Silicon Revision A) ................................... 17

Figure 1.5. Development/In-System Debug Diagram .............................................. 19

Figure 1.6. Memory Map ......................................................................................... 20

Figure 1.7. 12-Bit ADC Block Diagram .................................................................... 22

Figure 1.8. Comparator Block Diagram ................................................................... 23

Figure 1.9. Port I/O Functional Block Diagram ........................................................ 24

Figure 3.1. DFN-10 Pinout Diagram (Top View) ...................................................... 35

Figure 3.2. DFN-10 Package Diagram .................................................................... 38

Figure 3.3. DFN-10 Landing Diagram ..................................................................... 39

Figure 3.4. TSSOP-20 Pinout Diagram (Top View) ................................................. 40

Figure 3.5. TSSOP-20 Package Diagram ............................................................... 43

Figure 3.6. TSSOP-20 Landing Diagram ................................................................. 44

Figure 3.7. QFN-20 Pinout Diagram (Top View) ..................................................... 45

Figure 3.8. QFN-20 Package Diagram* ................................................................... 48

Figure 3.9. QFN-20 Landing Diagram* .................................................................... 50

Figure 4.1. ADC0 Functional Block Diagram ........................................................... 52

Figure 4.2. Typical Temperature Sensor Transfer Function .................................... 53

Figure 4.3. ADC0 Tracking Modes .......................................................................... 55

Figure 4.4. 12-Bit ADC Tracking Mode Example ..................................................... 56

Figure 4.5. 12-Bit ADC Burst Mode Example with Repeat Count Set to 4 .............. 58

Figure 4.6. ADC0 Equivalent Input Circuits ............................................................. 60

Figure 4.7. ADC Window Compare Example: 

Right-Justified Single-Ended Data ........................................................ 71

Figure 4.8. ADC Window Compare Example: 

Left-Justified Single-Ended Data .......................................................... 71

Figure 5.1. Voltage Reference Functional Block Diagram ....................................... 72

Figure 6.1. External Capacitors for Voltage Regulator Input/Output ....................... 74

Figure 7.1. Comparator Functional Block Diagram ................................................. 76

Figure 7.2. Comparator Hysteresis Plot .................................................................. 77

Figure 8.1. CIP-51 Block Diagram ........................................................................... 81

Figure 9.1. Memory Map ......................................................................................... 92

Figure 11.1. Reset Sources ................................................................................... 106

Figure 11.2. Power-On and VDD Monitor Reset Timing ........................................ 107

Figure 12.1. Flash Program Memory Map ............................................................. 117

Figure 13.1. Port I/O Functional Block Diagram .................................................... 120

Figure 13.2. Port I/O Cell Block Diagram .............................................................. 121

Figure 13.3. Crossbar Priority Decoder with No Pins Skipped 

(TSSOP 20 and QFN 20) .................................................................. 122

Figure 13.4. Crossbar Priority Decoder with Crystal Pins Skipped

(TSSOP 20 and QFN 20) .................................................................. 123

Rev. 1.4

7

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