LH28F004SUT-Z1 View Datasheet(PDF) - Sharp Electronics

Part Name

Description

Manufacturer

LH28F004SUT-Z1

4M (512K × 8) Flash Memory

Sharp Electronics 

LH28F004SU-Z1

4M (512K × 8) Flash Memory

INTRODUCTION

Sharp’s LH28F004SU-Z1 4M Flash Memory is a revo-

lutionary architecture which enables the design of truly

mobile, high performance, personal computing and com-

munication products. With innovative capabilities, 5 V

single voltage operation and very high read/write per-

formance, the LH28F004SU-Z1 is also the ideal choice

for designing embedded mass storage flash memory

systems.

The LH28F004SU-Z1 is a very high density, highest

performance non-volatile read/write solution for solid-

state storage applications. Its independently lockable

32 symmetrical blocked architecture (16K each)

extended cycling, low power operation, very fast write

and read performance and selective block locking pro-

vide a highly flexible memory component suitable for

high density memory cards, Resident Flash Arrays and

PCMCIA-ATA Flash Drives. The LH28F004SU-Z1’s

single power supply operation enables the design of

memory cards which can be read/written in 5.0 V sys-

tems. Its x8 architecture allows the optimization of

memory to processor interface. The flexible block lock-

ing option enables bundling of executable application

software in a Resident Flash Array or memory card.

Manufactured on Sharp’s 0.55 µm ETOX™ process

technology, the LH28F004SU-Z1 is the most cost-

effective, high-density 5.0 V flash memory.

Description

The LH28F004SU-Z1 is a high performance

4M (4,194,304 bit) block erasable non-volatile random

access memory organized as 512K × 8. The

LH28F004SU-Z1 includes thirty-two 16K (16,384)

blocks. A chip memory map is shown in Figure 3.

The implementation of a new architecture, with many

enhanced features, will improve the device operating

characteristics and results in greater product reliability

and ease of use.

Among the significant enhancements of the

LH28F004SU-Z1:

• 5 V Read, Write/Erase Operations (5 V VCC, VPP)

• Low Power Capability

• Improved Write Performance

• Dedicated Block Write/Erase Protection

• Command-Controlled Memory Protection

Set/Reset Capability

The LH28F004SU-Z1 will be available in a 40-pin,

1.2 mm thick × 10 mm × 20 mm TSOP (Type I) pack-

age.This form factor and pinout allow for very high board

layout densities.

A Commander User Interface (CUI) serves as the

system interface between the microprocessor or

microcontroller and the internal memory operation.

Internal Algorithm Automation allows Byte Writes and

Block Erase operations to be executed using a Two-

Write command sequence to the CUI in the same way

as the LH28F008SA 8M Flash Memory.

A Superset of commands have been added to the

basic LH28F008SA command-set to achieve higher

write performance and provide additional capabilities.

These new commands and features include:

• Software Locking of Memory Blocks

• Memory Protection Set/Reset Capability

• Two-Byte Successive Writes in 8-bit Systems

• Erase All Unlocked Blocks

Writing of memory data is performed typically within

13 µs. A Block Erase operation erases one of the 32

blocks in typically 0.6 seconds, independent of the other

blocks.

LH28F004SU-Z1 allows to erase all unlocked blocks.

It is desirable in case you have to implement Erase op-

eration maxmum 32 times.

LH28F004SU-Z1 enablesTwo-Byte serialWrite which

is operated by three times command input. This feature

can improve system write performance by up to typi-

cally 10 µs per byte.

All operations are started by a sequence of Write

commands to the device. Status Register (described in

detail later) and a RY »/BY » output pin provide informa-

tion on the progress of the requested operation.

Same as the LH28F008SA, LH28F004SU-Z1

requires an operation to complete before the next

operation can be requested, also it allows to suspend

block erase to read data from any other block, and al-

low to resume erase operation.

The LH28F004SU-Z1 provides user-selectable block

locking to protect code or data such as Device Drivers,

PCMCIA card information, ROM-Executable OS or

Application Code. Each block has an associated non-

volatile lock-bit which determines the lock status of the

block. In addition, the LH28F004SU-Z1 has a software

controlled master Write Protect circuit which prevents

any modifications to memory blocks whose lock-bits are

set.

4

Share Link: