LH28F004SUT-Z1 Datasheet PDF - Sharp Electronics

LH28F004SUT-Z1 View Datasheet(PDF) - Sharp Electronics

Part Name

Description

Manufacturer

LH28F004SUT-Z1

4M (512K × 8) Flash Memory

Sharp Electronics

LH28F004SUT-Z1 Datasheet PDF : 32 Pages

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4M (512K × 8) Flash Memory

LH28F004SU-Z1

When the device power-up or RP » turns High, Write

Protect Set/Confirm command must be written. Other-

wise, all lock bits in the device remain being locked,

can’t perform the Write to each block and single Block

Erase. Write Protect Set/Confirm command must be

written to reflect the actual lock status. However, when

the device power-on or RP » turns High, Erase All Un-

locked Blocks can be used. If used, Erase is performed

with reflecting actual lock status, and after that Write

and Block Erase can be used.

The LH28F004SU-Z1 contains Status Register to

accomplish various functions:

• A Compatible Status Register (CSR) which is

100% compatible with the LH28F008SA Flash

Memory’s Status Register. This register, when used

alone, provides a straightforward upgrade capabil-

ity to the LH28F004SU-Z1 from a LH28F008SA

based design.

The LH28F004SU-Z1 incorporates an open drain

RY »/BY » output pin. This feature allows the user to OR-

tie many RY/» BY» pins together in a multiple memory con-

figuration such as a Resident Flash Array.

The LH28F004SU-Z1 is specified for a maximum

access time of 100 ns (tACC) at 5 V operation (4.5 to

5.5 V) over the commercial temperature range (0 to

+70°C).

The LH28F004SU-Z1 incorporates an Automatic

Power Saving (APS) feature which substantially reduces

the active current when the device is in static mode of

operation (addresses not switching).

In APS mode, the typical ICC current is 2 mA at 5.0 V.

A Deep Power-Down mode of operation is invoked

when the RP » (called PWD on the LH28F008SA) pin

transitions low. This mode brings the device power con-

sumption to less than 5 µA, and provides additional write

protection by acting as a device reset pin during power

transitions. A reset time of 550 ns is required from RP »

switching high until outputs are again valid. In the Deep

Power-Down state, the WSM is reset (any current

operation will abort) and the CSR register is cleared.

A CMOS Standby mode of operation is enabled when

CE » transitions high and RP » stays high with all input

control pins at CMOS levels. In this mode, the device

draws an ICC standby current of 10 µA.

MEMORY MAP

7FFFFH

7C000H

7BFFFH

78000H

77FFFH

74000H

73FFFH

70000H

6FFFFH

6C000H

6BFFFH

68000H

67FFFH

64000H

63FFFH

60000H

5FFFFH

5C000H

5BFFFH

58000H

57FFFH

54000H

53FFFH

50000H

4FFFFH

4C000H

4BFFFH

48000H

47FFFH

44000H

43FFFH

40000H

3FFFFH

3C000H

3BFFFH

38000H

37FFFH

34000H

33FFFH

30000H

2FFFFH

2C000H

2BFFFH

28000H

27FFFH

24000H

23FFFH

20000H

1FFFFH

1C000H

1BFFFH

18000H

17FFFH

14000H

13FFFH

10000H

0FFFFH

0C000H

0BFFFH

08000H

07FFFH

04000H

03FFFH

00000H

16KB BLOCK

Figure 3. Memory Map

28F004SUT-Z1-3

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