MB15F07SLPV View Datasheet(PDF) - Fujitsu

Part Name

Description

Manufacturer

MB15F07SLPV

Dual Serial Input PLL Frequency Synthesizer

Fujitsu 

MB15F07SL

Table 8. LD/fout Output Select Data Setting

LDS

LD/fout output signal

H

fout (fr1/2, fp1/2) signals

L

LD signal

Table 9. Charge Pump Current Setting

CS

Current value

H

±6.0 mA

L

±1.5 mA

Power Saving Mode (Intermittent Mode Control Circuit)

Table 10. PS Pin Setting

PS pin

Status

H

Normal mode

L

Power saving mode

• The intermittent mode control circuit reduces the PLL power consumption. By setting the PS pin low, the device

enters into the power saving mode. See the Electrical Characteristics chart for the specific value.

• The phase detector output, Do, becomes high impedance.

• The lock detector ouput, LD, is as shown in the LD Output Logic Table on page 14.

• Setting the PS pin high releases the power saving mode, returning the selected PLL to normal operation.

• The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation.

When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is

because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr)

which can cause a major change in the comparator output, resulting in a VCO frequency jump and an increase

in lockup time.

• To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error

signal from the phase detector when it returns to normal operation.

Note: When power (VCC) is first applied, the device must be in standby mode, PS = Low, for at least 1 µs.

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