MB15F07SLPV View Datasheet(PDF) - Fujitsu

Part Name

Description

Manufacturer

MB15F07SLPV

Dual Serial Input PLL Frequency Synthesizer

Fujitsu 

MB15F07SL

Programmable Counter

LSB

Data Flow

MSB

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

C

N

1

C

N

2

LSF

DWC

S 1/2 1/2

A

1

A

2

A

3

A

4

A

5

A

6

A

7

N

1

N

2

N

3

N

4

N

5

N

6

N

7

N

8

NNN

9 10 11

CNT1, 2 : Control bits

N1 to N11: Divide ratio setting bits for the programmable counter (3 to 2,047)

A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127)

SW1/2 : Divide ratio setting bit for the prescaler

(64/65 or 128/129 for both SW1 and SW2)

FC1/2

: Phase control bit for the phase detector (PLL 1: FC1, PLL 2: FC2)

LDS

: LD/fout signal select bit

NOTE: Input data with MSB first.

[Table 1]

[Table 4]

[Table 5]

[Table 6]

[Table 7]

[Table 8]

Table 2. Binary 14-bit Programmable Reference Counter Data Setting

Divide

ratio

(R)

RRRRRRRRRRRRRR

14 13 12 11 10 9 8 7 6 5 4 3 2 1

3

00000000000011

4

00000000000100

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

16383

11111111111111

Note: • Divide ratio less than 3 is prohibited.

Table 3. Test Purpose Bit Setting

T

T

1

2

LD/fout pin state

L

L

Outputs fr1.

H

L

Outputs fr2.

L

H

Outputs fp1.

H

H

Outputs fp2.

9

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