MB40730 View Datasheet(PDF) - Fujitsu
Part Name
Description
Manufacturer
MB40730 Datasheet PDF : 16 Pages
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MB40730
s PIN ASSIGNMENT
(MSB)
(LSB)
(TOP VIEW)
D1
1
D2
2
D3
3
D4
4
D5
5
D6
6
D7
7
D8
8
D9
9
D10
10
20 CLK
19
VCCD
18
VCCA
17 A.OUT
16
VROUT2
15
VRIN
14
VROUT1
13 COMP
12
VEEA
11
VEED
(DIP-20P-M01)
(FPT-20P-M01)
s PIN DESCRIPTIONS
Pin No.
Symbol
I/O
1 to 10
D1 to D10
I
20
CLK
I
19
VCCD
-
18
VCCA
-
11
VEED
-
12
VEEA
-
15
VRIN
I
14
VROUT1
O
16
VROUT2
O
13
COMP
-
17
A. OUT
O
Description
Data signal input pin (D1: MSB, D10: LSB)
Clock signal input pin
Digital ground pin (0 V)
Analog ground pin (0 V)
Digital power pin (-5.2 V)
Analog ground pin (-5.2 V)
Reference voltage input pin
Analog output dynamic range setup pin
Connect to pin 14 or 16 to use the built-in reference voltage
When using an external reference voltage, the voltage on this pin must be from
-2.20 V to -0.70 V
Reference voltage output pin 1
The output voltage of the potential divider reference is fixed at VEEA 2/5.2. When this
pin is connected to pin 15, the analog output voltage ranges from VEEA 2/5.2 to 0 V
Reference voltage output pin 2
The output voltage of the band-gap reference is fixed at -2.0 V. When the
pin is connected to pin 15, the analog output voltage ranges from -2 V to 0 V
Phase compensation capacitor pin
Insert a capacitor of 0.1 µF or greater between VEEA and COMP for phase
compensation
Analog signal output pin
2
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