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MGA-87563-BLKG View Datasheet(PDF) - Avago Technologies

Part Name
Description
Manufacturer
MGA-87563-BLKG
AVAGO
Avago Technologies AVAGO
MGA-87563-BLKG Datasheet PDF : 9 Pages
1 2 3 4 5 6 7 8 9
MGA-87563 Applications Information
Introduction
The MGA-87563 low noise RF amplifier is designed to
simplify wireless RF applications in the 0.5 to 4 GHz
frequency range. The MGA-87563 is a two-stage, GaAs
Microwave Monolithic Integrated Circuit (MMIC) amplifier
that uses feedback to provide wideband gain. The output
is matched to 50Ω and the input is partially matched for
optimum noise figure.
A patented, active bias circuit makes use of current sources
to “re-use” the drain current in both stages of gain, thus
minimizing the required supply current and decreasing
sensitivity to variations in power supply voltage.
Test Circuit
The circuit shown in Figure 10 is used for 100% RF testing
of Noise Figure and Gain. The input of this circuit is fixed
tuned for a conjugate power match (maximum power
transfer, or, minimum Input VSWR) at 2 GHz. Tests in this
circuit are used to guarantee the NFtest and Gtest parameters
shown in the Electrical Specifications table.
The 4.7 nH inductor, L1 (Coilcraft, Cary, IL part number series
1008CT-040) placed in series with the input of the amplifier
is all that is necessary to match the input to 50Ω at 2 GHz.
Vdd
C1
RF
INPUT
L1
50 Ω 4.7 nH
10 Ω
RF
OUTPUT
50 Ω
Figure 10. Test Circuit for 2 GHz.
Phase Reference Planes
The positions of the reference planes used to measure
S-Parameters and to specify opt for the Noise Parameters
are shown in Figure 11. As seen in the illustration, the
reference planes are located at the extremities of the
package leads.
REFERENCE
PLANES
Biasing
The MGA-87563 is a voltage-biased device and operates
from a single +3 volt power supply. With a typical current
drain of only 4.5 mA, the MGA-87563 is very well suited
for use in battery powered applications. All bias regula-
tion circuitry is integrated into the MMIC, eliminating the
need for external DC components. RF performance is very
consistent for 3-volt battery supplies that may range from
2.7 to 3.3 volts, depending on battery “freshness” or state
of charge for rechargeable batteries. Operation up to +5
volts is discussed at the end of the Applications section.
The test circuit in Figure 10 illustrates a suitable method for
bringing bias into the MGA-87563. The bias connection
must be designed so that it adequately bypasses the Vdd
terminal while not inadvertently creating any resonances
at frequencies where the MGA-87563 has gain.
The 10Ω resistor, R1, serves to “de-Q” any potential
resonances in the bias line that could lead to low gain,
unwanted gain variations or device instability. The power
supply end of R1 is bypassed to ground with capacitor C1.
The suggested value for C1 is 100 pF. Significantly higher
values for C1 are not recommended. Many higher value
chip capacitors (e.g., 1000 pF) are not of sufficiently high
quality at these frequencies to function well as a RF bypass
without adding harmful parasitics or self-resonances.
While the input and output terminals are internally resis-
tively grounded, these pins should not be considered to be
current sinks. Connection of the MGA-87563 amplifier to
circuits that are at ground potential may be made without
the additional cost and PCB space needed for DC blocking
capacitors. If the amplifier is to be cascaded with active
circuits having non-zero voltages present, the use of series
blocking capacitors is recommended.
Input Matching
The input of the MGA-87563 is partially matched internally
to 50 Ω. The use of a simple input conjugate matching
circuit (such as shown in Figure 10 for 2 GHz), will lower
the noise figure considerably. A significant advantage of
the MGA-87563’s design is that the impedance match for
NFo (minimum noise figure) is very close to a conjugate
power match. This means that a very low noise figure can
be realized simultaneously with a low input VSWR. The
typical difference between the noise figure obtainable
with a conjugate power match at the input and NFo is
only about 0.2 dB.
TEST CIRCUIT
Figure 11. Reference Planes.
5

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