MA82380 View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

MA82380

HIGH PERFORMANCE 32-BIT DMA CONTROLLER WITH INTEGRATED SYSTEM SUPPORT PERIPHERALS

Intel 

M82380

Table 3 Output Signals Following RESET

Signal

Level

A2– A31 D0–D31 BE0 –BE3

D C W R M IO ADS

READYO

EOP

EDACK2 – EDACK0

HOLD

INT

TOUT1 REF TOUT2 IRQ3 TOUT3

CPURST

Float

Float

‘1’

‘1’ (Weak Pull-UP)

‘100’

‘0’

UNDEFINED

UNDEFINED

‘0’

The Interrupt Controller and Programmable Interval Timer are initialized by software commands

processor The M82380 is reset by asserting RESET

for 15 or more CLK2 periods When RESET is as-

serted all other input pins are ignored and all other

bus pins are driven to an idle bus state as shown in

Table 3 The M82380 will determine the phase of its

internal clock following RESET going inactive

RESET is level-sensitive and must be synchronous

to the CLK2 signal Therefore this RESET input

should be tied to the RESET output of the Clock

Generator The RESET setup and hold time require-

ments are shown in Figure 8

CPURST

This output signal is used to reset the i386 host

processor It will go active (HIGH) whenever one of

the following events occurs a) M82380’s RESET in-

put is active b) a software RESET command is is-

sued to the M82380 or c) when the M82380 detects

a processor Shutdown cycle and when this detec-

tion feature is enabled (see CPU Reset and Shut-

down Detect) When activated CPURST will be held

active for 62 CLK2 periods The timing of CPURST is

such that the i386 processor will be in synchroniza-

tion with the M82380 This timing is shown in

Figure 9

T30-RESET Hold Time

T31-RESET Setup Time

Figure 8 RESET Timing

271070 – 9

T33-CPU Reset from CLK2

Figure 9 CPURST Timing

16

271070 – 10

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