NX25F640C-3T View Datasheet(PDF) - NexFlash -> Winbond Electronics

Part Name

Description

Manufacturer

NX25F640C-3T

64M-BIT SERIAL FLASH MEMORY WITH 4-PIN SPI INTERFACE

NexFlash -> Winbond Electronics 

NX25F640C

Command Set

The NX25F640C has a powerful command set that is fully

controlled through the SPI bus. Command relationships

are shown in Figure 4 and a list of commands and their

associated address, status, clock, and data bytes are

shown in the Command Set Table on page 13. Flow

diagrams for writing to a sector and reading from a sector

are shown in Figures 7 and 8. Detailed clock timing of the

Write to Sector using SRAM, Transfer Sector to SRAM

and Read SRAM command sequences are shown in Fig-

ures 9, 10 and 11.

After power up, a device enters an idle state that will main-

tain until CS pin is asserted low. Chip reset is defined as a

low to high transition of CS. Thus, to reset the chip at power

on, a high to low to high transition is required. A command

may start after a high to low transition of CS. When a

command is started, CS needs to stay low for the

duration of the command and data.

Start Read Sector Routine

Read Status Register for

Ready/Busy Status

(ST15, ST14, ST13)

(Command: 84H)

Yes

Busy ?

No

Transfer Sector Data

To SRAM-0/1

(Command: 5CH/5DH)

Read Status (ST15:0)

For Ready/Busy and Data Integrity

(DI0, DI1)

Read Data From SRAM-0/1

(Command: 71H/73H)

Return

Figure 7. Read data from sector

12

Start Write Sector Routine

Write Enable Flash Array

(Command: 06H)

Read Status Register for

Read/Busy Status

(ST15, ST14, ST13)

(Command: 84H)

Yes

Busy ?

No

Write 522 Bytes Data

To Sector Using SRAM-0/1

(Command: F6H/98H)

(Optional)

Write-Disable Flash Array

(Command: 04H)

Return

Figure 8. Write data to sector (Erase + Program)

NexFlash Technologies, Inc.

PRELIMINARY NXSF022F-0502

05/20/02 ©

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