PEEL18LV8Z View Datasheet(PDF) - International Cmos Technology
Part Name
Description
Manufacturer
PEEL18LV8Z Datasheet PDF : 10 Pages
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switching long enough to trigger the next power-down.
(Note that the tPD is approximately 5 ns. slower on the first
transition from sleep mode.)
As a result of the "Zero-Power" feature, significant power
savings can be realized for combinatorial or sequential
operations when the inputs or clock change at a modest
rate. See Figure 6.
When the PEEL18LV8Z is powered up, a built-in feature
holds the outputs in tri-state until Vcc reaches 2.2V. This
prevents output transitions during power-up.
Figure 5 - Equivalent Circuits for the twelve configurations of the PEEL18LV8Z I/O Macrocell
Configuration
#
ABCD
Input/Feedback Select
Output Select
1
0010
2
1
0
1
0 Bi-directional I/O
3
0100
4
1100
5
0011
6
1
0
1
1 Combinatorial Feedback
7
0111
8
1111
9
0000
10
10
0
0 Register Feedback
11
01
1
0
12
11
1
0
Register
Combinatorial
Register
Combinatorial
Register
Combinatorial
Active Low
Active High
Active Low
Active High
Active Low
Active High
Active Low
Active High
Active Low
Active High
Active Low
Active High
Anachip Corp.
www.anachip.com.tw
Rev. 1.0 Dec 16, 2004
5/10
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