RC5042 View Datasheet(PDF) - Fairchild Semiconductor
Part Name
Description
Manufacturer
RC5042 Datasheet PDF : 20 Pages
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RC5042
PRODUCT SPECIFICATION
5V
2.5µH
0.1µF
Vin
1000µF, 10V
Electrolytic
65-AP42-17
Figure 8. Input Filter
PCB Layout Guidelines and
Considerations
PCB Layout Guidelines
1. Placement of the MOSFETs relative to the RC5042 is
critical. The MOSFETs (M1 & M2), should be placed
such that the trace length of the HIDRV pin from the
RC5042 to the FET gates is minimized. A long lead
length on this pin will cause high amounts of ringing due
to the inductance of the trace combined with the large
gate capacitance of the FET. This noise will radiate all
over the board, and because it is switching at such a high
voltage and frequency, it will be very difficult to sup-
press.
The drawing below depicts an example of good place-
ment for the MOSFETs in relation to the RC5042
and also an example of problematic placement for the
MOSFETs.
In general, all of the noisy switching lines should be kept
away from the quiet analog section of the RC5042. That
is to say, traces that connect to pins 8 and 9 (HIDRV and
VCCQP) should be kept far away from the traces that
connect to pins 1 through 4, and pin 12.
2. Place decoupling capacitors (.1mF) as close to the
RC5042 pins as possible. Extra lead length on these will
negate their ability to suppress noise.
3. Each VCC and GND pin should have its own via down
to the appropriate plane underneath. This will help give
isolation between pins.
4. Surround the CEXT timing capacitor with a ground
trace as much as possible. Also be sure to keep a ground
or power plane underneath the capacitor for further noise
isolation. This will help to shield the oscillator pin 1
from the noise on the PCB. Place this capacitor as close
to the RC5042 pin 1 as possible.
5. Place MOSFETs, inductor and Schottky as close
together as possible for the same reasons as #1 above.
Place the input bulk capacitors as close to the drains of
MOSFETs as possible. In addition, placement of a
0.1mF decoupling cap right on the drain of each MOS-
FET will help to suppress some of the high frequency
switching noise on the input of the DC-DC converter.
6. The traces that run from the RC5042 IFB (pin 3) and
VFB (pin 4) pins should be run together next to each
other and be Kelvin connected to the sense resistor. Run-
ning these lines together will help in rejecting some of
the common noise that is presented to the RC5042 feed-
M1
M2
Correct layout
9
8
10
7
11
6
12
5
13
4
14
3
15
2
16
1
Poor layout
9
8
10
7
11
6
12
5
13
4
14
3
15
2
16
1
= “Quiet" Pins
M1
M2
Figure 9. MOSFET Layout Guidelines
16
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