RC5042 View Datasheet(PDF) - Fairchild Semiconductor
Part Name
Description
Manufacturer
RC5042 Datasheet PDF : 20 Pages
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RC5042
Pin Assignments
CEXT
PWRGD
IFB
VFB
VCCA
VCCD
GNDP
HIDRV
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
65-5042-02
VID0
VID1
VID2
VID3
VREF
GNDA
GNDD
VCCQP
PRODUCT SPECIFICATION
Pin Definitions
Pin Number Pin Name Pin Function Description
1
CEXT Oscillator capacitor connection. Connecting an external capacitor to this pin sets
the internal oscillator frequency from 200 KHz to 1 MHz. Layout of this pin is critical to
system performance. See Application Information for details.
2
PWRGD Power Good output flag. Open collector output will be at logic HIGH under normal
operation. Logic LOW indicates output voltage is not within ±10% of nominal.
3
IFB High side current feedback. Pins short 4 and 5 are used as the inputs for the current
feedback control loop and as the short circuit current sense points. Layout of these
traces is critical to system performance. See Application Information for details.
4
VFB Voltage feedback. Pin 5 is used as the input for the voltage feedback control loop and
as the low side current feedback input. Layout of this trace is critical to system
performance. See Application Information for details.
5
VCCA Analog VCC. Connect to system 5V supply and decouple to ground with 0.1mF
ceramic capacitor.
6
VCCD Digital VCC. Connect to system 5V supply and decouple to ground with 4.7mF
tantalum capacitor.
7
GNDP Power ground. Return pin for high currents flowing in pins 8 and 9 (HIDRV and
VCCQP). Connect to low impedance ground. See Application Information for details.
8
HIDRV FET driver output. Connect this pin to the gate of the N-channel MOSFETs M1 and
M2 in Figures 1 and 2. The trace from this pin to the MOSFET gates should be kept as
short as possible (less than 0.5"). See Application Information for details.
9
VCCQP Power VCC for FET Driver. VCCQP must be connected to a voltage of at least
VCCA + VGS,ON (M1). See Application Information for details.
10
GNDD Digital ground. Return path for digital logic. This pin should be connected to system
ground so that ground loops are avoided. See Application Information for details.
11
GNDA Analog ground. Return path for low power analog circuitry. Connect to system ground
so that ground loops are avoided. See Application Information for details.
12
VREF Reference voltage test point. This pin provides access to the DAC output and
should be decoupled to ground using a 0.1mF capacitor. No load should be connected
to this pin.
13–16
VID3–
VID0
Voltage identification (VID) code inputs. These open collector/TTL compatible
inputs will program the output voltage over the ranges specified in Table 1. Internal
10KW pull-up resistors assure correct operation if pins are left unconnected.
2
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