Specifications ispLSI 1016E
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER
TEST 4
COND.
#2
DESCRIPTION1
-125
-100
-80
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
tpd1
A 1 Data Prop. Delay, 4PT Bypass, ORP Bypass
– 7.5 – 10.0 – 15.0 ns
tpd2
fmax
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
A
A
–
–
–
A
–
–
–
2 Data Prop. Delay, Worst Case Path
3 Clk. Frequency with Int. Feedback3
4
Clk.
Frequency
with
Ext.
( Feedback
1
tsu2 +
) tco1
5
Clk.
Frequency,
Max.
Toggle(
1
twh +
) tw1
6 GLB Reg. Setup Time before Clk., 4 PT Bypass
7 GLB Reg. Clk. to Output Delay, ORP Bypass
8 GLB Reg. Hold Time after Clk., 4 PT Bypass
9 GLB Reg. Setup Time before Clk.
10 GLB Reg. Clk. to Output Delay
–
125
100
167
5.0
–
0.0
5.5
–
10.0
–
–
–
–
4.5
–
–
5.5
– 13.0 – 18.5
100 – 84.0 –
S 77.0 – 57.0 –
N 125 – 100 –
IG 7.0 – 8.5 –
– 5.0 – 8.0
S 0.0 – 0.0 –
E 8.0 – 9.5 –
D– 6.0 – 9.5
ns
MHz
MHz
MHz
ns
ns
ns
ns
ns
th2
tr1
trw1
tptoeen
– 11 GLB Reg. Hold Time after Clk.
A 12 Ext. Reset Pin to Output Delay
– 13 Ext. Reset Pulse Duration
B 14 Input to Output Enable
0.0 – 0.0
W – 10.0 –
E5.0 – 6.5
N– 12.0 –
– 0.0
13.5 –
– 10.0
15.0 –
–
17.0
–
20.0
ns
ns
ns
ns
tptoedis
tgoeen
tgoedis
twh
C
B
C
–
15 Input to Output Disable
R 16 Global OE Output Enable
17 Global OE Output Disable
FO 18 Ext. Sync. Clk. Pulse Duration, High
–
–
–
3.0
12.0
7.0
7.0
–
–
–
–
4.0
15.0
9.0
9.0
–
–
–
–
5.0
20.0
10.5
10.5
–
ns
ns
ns
ns
twl
A tsu3
E th3
– 19 Ext. Sync. Clk. Pulse Duration, Low
3.0 – 4.0
– 20 I/O Reg. Setup Time before Ext. Sync. Clk. (Y2, Y3) 3.0 – 3.5
– 21 I/O Reg. Hold Time after Ext. Sync. Clk. (Y2, Y3) 0.0 – 0.0
6 1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
1 3. Standard 16-bit counter using GRP feedback.
ispLSI 10 4. Reference Switching Test Conditions Section.
–
–
–
5.0 –
ns
4.5 –
ns
0.0 –
ns
Table 2-0030-16/125,100, 80
USE
5