ISPLSI1016E-100LT44 View Datasheet(PDF) - Lattice Semiconductor

Part Name

Description

Manufacturer

ISPLSI1016E-100LT44

In-System Programmable High Density PLD

Lattice Semiconductor 

Specifications ispLSI 1016E

ispLSI 1016E Timing Model

I/O Cell

GRP

GLB

ORP

I/O Cell

Feedback

Ded. In

I/O Pin

(Input)

#59

#28

I/O Reg Bypass

#22

Input

D Register Q

RST

#23 - 27

Reset

Y1,2

#30

GRP

Loading

Delay

#29, 31, 32

Clock

Distribution

#55-58

Comb 4 PT Bypass #34

Reg 4 PT Bypass

#35

20 PT

XOR Delays

#36-38

#59

GLB Reg Bypass

#39

GLB Reg

Delay

D

Q

RST

#40-43

Control RE

PTs OE

#44-46 CK

ORP Bypass

#48

ORP

S Delay

DESIGN #47

#49, 50

#51, 52

I/O Pin

(Output)

#54

Y0

#53

GOE 0

Derivations of tsu, th and tco from the Product Term Clock1

NEW

0491-16

tsu

= Logic + Reg su - Clock (min)

= (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min))

R = (#22 + #30 + #37) + (#40) - (#22 + #30 + #46)

1.4 ns = (0.3 + 1.9 + 4.4) + (0.2) - (0.3 + 1.9 + 3.2)

FO th

= Clock (max) + Reg h - Logic

= (tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor)

= (#22 + #30 + #46) + (#41) - (#22 + #30 + #37)

A 0.6 ns = (0.3 + 1.9 + 3.5) + (1.5) - (0.3 + 1.9 + 4.4)

E tco

= Clock (max) + Reg co + Output

6 = (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob)

1 = (#22 + #30 + #46) + (#42) + (#47 + #49)

0 9.9 ns = (0.3 + 1.9 + 3.5) + (1.8) + (1.0 + 1.4)

I 1 Derivations of tsu, th and tco from the Clock GLB1

tsu

= Logic + Reg su - Clock (min)

S = (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgy0(min) + tgco + tgcp(min))

L = (#22 + #30 + #37) + (#40) - (#54 + #42 + #56)

p 2.9 ns = (0.3 + 1.9 + 4.4) + (0.2) - (1.3 + 1.8 + 0.8)

is th

= Clock (max) + Reg h - Logic

= (tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor)

= (#54 + #42 + #56) + (#41) - (#22 + #30 + #37)

E-0.2 ns = (1.3 + 1.8 + 1.8) + (1.5) - (0.3 + 1.9 + 4.4)

Stco

= Clock (max) + Reg co + Output

U = (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob)

= (#54 + #42 + #56) + (#42) + (#47 + #49)

9.1 ns = (1.3 + 1.8 + 1.8) + (1.8) + (1.0 + 1.4)

Table 2-0042-16

1. Calculations are based upon timing specifications for the ispLSI 1016E-125

8

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