P87CL881H View Datasheet(PDF) - Philips Electronics

Part Name

Description

Manufacturer

P87CL881H

Low-voltage microcontroller with 63-kbyte OTP program memory and 2-kbyte RAM / LQFP44 Package

Philips Electronics 

Philips Semiconductors

Low-voltage microcontroller with 63-kbyte

OTP program memory and 2-kbyte RAM

Product specification

P87CL881H

REGISTER NAME

REGISTER MNEMONIC

OTP interface

OTP Address High Register

OTP Address Low Register

OTP Data Register

OTP In-System Programming Register

OTP Test Register

OAH

OAL

ODATA

OISYS

OTEST

Notes

1. E7H and FDH are reserved locations and must not be written to.

2. Where: X = undefined state.

SFR ADDRESS

D5

D4

D6

DC

D7

RESET VALUE(2)

X00X XXXX

XXXX XXXX

XXXX XXXX

000X 0000

0000 0000

6.2 I/O facilities

6.2.1 PORTS

The P87CL881 has 32 I/O lines treated as 32 individually

addressable bits or as four parallel 8-bit addressable ports.

Ports 0, 1, 2 and 3 perform the following alternative

functions:

Port 0 Provides the multiplexed low-order address and

data bus for expanding the device with standard

memories and peripherals.

Port 1 Used for a number of special functions:

• P1.0 to P1.7 provides the inputs for the external

interrupts INT2 to INT9

• P1.0/T2 and P1.1/T2EX for external inputs of Timer 2

• P1.2/T2COMP for external activation and compare

output of Timer 2

• P1.4/CLK for the clock output

• P1.6/SCL and P1.7/SDA for the I2C-bus interface are

real open-drain outputs or high-impedance; no other

port configurations are available.

Port 2 Provides the high-order address bus when

expanding the device with external program

memory and/or external data memory.

Port 3 Pins can be configured individually to provide:

• P3.0/RXD/data and P3.1/TXD/clock which are serial

port receiver input and transmitter output (UART)

• P3.2/INT0 and P3.3/INT1 are external interrupt request

inputs

• P3.4/T0 and P3.5/T1 as counter inputs

• P3.6/WR and P3.7/RD are control signals to write and

read to external memories.

To enable a port pin alternative function, the port bit latch

in its SFR must contain a logic 1.

Each port consists of a latch (Special Function Registers

P0 to P3), an output driver and input buffer. All ports have

internal pull-ups. Figure 3(a) shows that the strong

transistor P1 is turned on for only 1 oscillator period after a

LOW-to-HIGH transition in the port latch. When on, it turns

on P3 (a weak pull-up) through the inverter IN1. This

inverter and transistor P3 form a latch which holds the

logic 1.

6.2.2 PORT I/O CONFIGURATION

I/O port output configurations are determined by the

settings in the port configuration SFRs. Each port has two

associated SFRs: PnCFGA and PnCFGB, where ‘n’

indicates the specific port number (0 to 3). One bit in each

of the 2 SFRs relates to the output setting for the

corresponding port pin, allowing any combination of the

2 output types to be mixed on those port pins.

For example, the output type of P1.3 is controlled by

setting bit 3 in the SFRs P1CFGA and P1CFGB.

The port pins may be individually configured via the SFRs

with one of the following modes (P1.6 and P1.7 can be

open-drain or high-impedance but never have any diodes

against VDD).

Mode 0 Open-drain; quasi-bidirectional I/O with

n-channel open-drain output. Use as an output

(e.g. Port 0 for external memory accesses

(EA = 0) or access above the built-in memory

boundary) requires the connection of an external

pull-up resistor. The ESD protection diodes

against VDD and VSS are still present. Except for

the I2C-bus pins P1.6 and P1.7, ports which are

configured as open-drain still have a protection

diode to VDD. See Fig.3a.

1999 Apr 16

10

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