SC1480A View Datasheet(PDF) - Semtech Corporation
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SC1480A Datasheet PDF : 23 Pages
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SC1480A
POWER MANAGEMENT
Applications Information (Cont.)
The on pulse in the SC1480A is calculated to give a
pseudo fixed frequency. Nevertheless, some frequency
variation with line and load can be expected. This variation
changes the output ripple voltage. Because constant on
regulators regulate to the valley of the output ripple, ½
of the output ripple appears as a DC regulation error.
.or example, if RE.OUT=0.9V, then the valley of the
output ripple will be 0.9V. If the ripple is 20mV with VBAT
= 6V, then the DC output voltage will be 0.91V. If the
ripple is 30mV with VBAT = 25V, then the DC output
voltage will be 0.915V.
The output inductor value may change with current. This
will change the output ripple and thus the DC output
voltage. It will not change the frequency.
Switching frequency variation with load can be minimized
by choosing MOS.ETs with lower RDS(ON). High RDS(ON)
MOS.ETs will cause the switching frequency to increase
as the load current increases. This will reduce the ripple
and thus the DC output voltage.
Input (VBAT) Supply Selection
The SC1480A can be configured so that VTT is generated
directly from the battery. Alternatively, VTT can be
generated from VDDQ. Since the battery configuration
generally yields better overall efficiency and performance,
the recommended method is to generate VTT from the
battery.
Design Procedure
Prior to designing an output and making component
selections, it is necessary to determine the input voltage
range and the output voltage specifications. .or purposes
of demonstrating the procedure the VTT output for the
schematic in .igure 3 on Page 14 will be designed.
+/-40mV, or 4.44%, we will design for 4%)
3) transient tolerance, TOLTR and size of transient (for
DDR2 this is undefined, so assume +/-8% for purposes
of this demonstration).
4) maximum output current, IOUT (we will design for 3A)
Switching frequency determines the trade-off between
size and efficiency. Increased frequency increases the
switching losses in the MOS.ETs, since losses are a
function of VIN2. Knowing the maximum input voltage and
budget for MOS.ET switches usually dictates where the
design ends up. A default RtON value of 715kΩ is
suggested as a starting point, but this is not set in stone.
The first thing to do is to calculate the on-time, tON, at
VBAT(MIN) and V , BAT(MAX) since this depends only upon VBAT,
VOUT and RtON. .or VOUT < 3.3V:
( )
tON _ VBAT(MIN) = 3.3 • 10−12 • RtON + 37 • 103
•
VOUT
VBAT (MIN)
+
50
• 10−9
s
.rom this value of tON we can calculate the nominal
switching frequency as follows:
( ) f = V V• t Hz SW _ VBAT(MIN)
OUT
BAT(MIN) ON _ VBAT(MIN)
and
( ) f = V V• t Hz SW _ VBAT(MAX)
OUT
BAT(MAX ) ON _ VBAT(MAX )
tON is generated by a one-shot comparator that samples
VBAT via RtON, converting this to a current. This current is
used to charge an internal 3.3p. capacitor to VOUT. The
equations above reflect this along with any internal
components or delays that influence tON. .or our DDR2
VTT example we select RtON = 715kΩ:
The maximum input voltage (VBAT(MAX)) is determined by
the highest AC adaptor voltage. The minimum input
voltage (VBAT(MIN)) is determined by the lowest battery
voltage after accounting for voltage drops due to
connectors, fuses and battery selector switches. .or the
purposes of this design example we will use a VBAT range
of 8V to 20V.
.our parameters are needed for the output:
1) nominal output voltage, VOUT (for DDR2 this is 0.9V)
2) static (or DC) tolerance, TOLST (for DDR2 this is
tON_VBAT(MIN) = 329ns and tON_VBAT(MAX) = 162ns
fSW_VBAT(MIN) = 342kHz and fSW_VBAT(MAX) = 278kHz
Now that we know tON we can calculate suitable values
for the inductor. To do this we select an acceptable
inductor ripple current. The calculations below assume
50% of IOUT which will give us a starting place.
2003 Semtech Corp.
10
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