SK100E016PJ(2002) View Datasheet(PDF) - Semtech Corporation
Part Name
Description
Manufacturer
SK100E016PJ Datasheet PDF : 9 Pages
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TEST AND MEASUREMENT PRODUCTS
Description
Features
SK100E016
8-Bit Synchronous
Binary Up Counter
The SK100E016 is a high-speed synchronous, • 700 MHz Minimum Count Frequency
presettable, cascadable 8-bit binary counter.
• 835 ps CLK to Q, TC*
• Internal TC* Feedback (Gated)
The counter features internal feedback of TC*, gated by • 8-Bit
the TCLD (terminal count load) pin. When TCLD is LOW • Fully Synchronous Counting and TC* Generation
(or left open, in which case it is pulled LOW by the internal • Asynchronous Master Reset
pull-downs), the TC* feedback is disabled, and counting • Internal 75 kΩ Input Pulldown Resistors
proceeds continuously, with TC* going LOW to indicate • Extended 100E VEE Range of –4.2V to –5.5V
an all-one state. When TCLD is HIGH, the TC* feedback • Fully Compatible with MC100E016
causes the counter to automatically reload upon TC* = • Available in 28-Pin PLCC Package
LOW, thus functioning as a programmable counter. The • ESD Protection of >4000V
Qn outputs do not need to be terminated for the count
function to operate properly. To minimize noise and
power, unused Q outputs should be left unterminated.
Functional Block Diagram
8 Bit Binary Counter - Logic Counter
Q0
PE
TCLD
QOM
CE*
MASTER
SLAVE
CE*
BIT 0
QOM*
Q0*
PO
P1
MR
CLK
Q1
BIT 1
CE*
Q0*
Q1*
Q2*
Q3*
Q4*
Q5*
Q6*
P7
BITS 2-6
5
Q7
BIT 7
TC*
Note that this diagram is provided for understanding of logic operation only. It should not be used for propagation
delays as many gate functions are achieved internally without incurring a full gate delay.
Revision 2/ September 5, 2002
1
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