TQ2060 View Datasheet(PDF) - TriQuint Semiconductor
Part Name
Description
Manufacturer
TQ2060 Datasheet PDF : 6 Pages
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TQ2060
Table 5. AC Characteristics (VDD = +5 V + 5%, TA = 0 °C to +70 °C)
Symbol
tCPWH
tCPWL
tIR
Input Clock (REFCLK)
CLK pulse width HIGH
CLK pulse width LOW
Input rise time (0.8 V – 2.0 V)
Test Conditions (Figure 5)
Figure 5
Figure 5
Min Typ Max Unit
4
—
—
ns
4
—
—
ns
—
—
2.0
ns
Symbol
tOR, tOF
tCYC
tJP2
tSYNC3
Output Clock (Q, QN)
Rise/fall time (20% – 80%)
Duty-cycle
Period-to-Period Jitter
Synchronization Time
Test Conditions (Figures 4 & 5)1 Min
Figure 5
100
Figure 5
45
—
—
Typ Max Unit
220 350
ps
50
55
%
25
70
ps
10
500
µs
Notes: 1. All measurements are tested with a REFCLK having a rise time of 0.5 ns (0.8 V to 2.0 V).
2. Jitter specification is peak to peak. Period-to-Period jitter is the jitter on the output with respect to the output's previous crossing.
3. tSYNC is the time required for the PLL to synchronize and assumes the presence of a CLK signal.
Figure 4. PECL Test Load
Figure 5. REFCLK and Q-QN Timing
4
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