FS6370 View Datasheet(PDF) - AMI Semiconductor
Part Name
Description
Manufacturer
FS6370 Datasheet PDF : 25 Pages
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FS6370-01
EEPROM Programmable 3-PLL Clock Generator IC
5.0 Run Mode
If the MODE pin is set to a logic-high, the device enters
the Run Mode. The high state is latched (see MODE Pin).
The FS6370 then copies the stored EEPROM data into
its control registers and begins normal operation based
on that data when the self-load is complete.
The self-load process takes about 89,000 clocks of the
crystal oscillator. During the self-load time, all clock out-
puts are held low. At a reference frequency of 27MHz,
the self-load takes about 3.3ms to complete.
If the EEPROM is empty (all zeros), the crystal reference
frequency provides the clock for all four outputs.
No external programming access to the FS6370 is possi-
ble in Run Mode. The dual-function PD/SCL and OE/SDA
pins become a power-down (PD) and output enable (OE)
control, respectively.
5.1 Power-Down and Output Enable
A logic-high on the PD/SCL pin powers down only those
portions of the FS6370 which have their respective
power-down control bits enabled. Note that the PD/SCL
pin has an internal pull-up.
When a Post Divider is powered down, the associated
output driver is forced low. When all PLLs and Post Di-
viders are powered down the crystal oscillator is also
powered down. The XIN pin is forced low, and the XOUT
pin is pulled high.
A logic-low on the OE/SDA pin tristates all output clocks.
Note that this pin has an internal pull-up.
6.0 Program Mode
If the MODE pin is logic-low, the device enters the Pro-
gram Mode. All internal registers are cleared to zero, de-
livering the crystal frequency to all outputs. The device
allows programming of either the internal 128-bit
EEPROM or the on-chip control registers via I2C control
over the PD/SCL and OE/SDA pins. The EEPROM and
the FS6370 act as two separate parallel devices on the
same on-chip I2C-bus. Choosing either the EEPROM or
the device control registers is done via the I2C device
address.
The dual-function PD/SCL and OE/SDA pins become the
serial data I/O (SDA) and serial clock input (SCL) for
normal I2C communications. Note that power-down and
output enable control via the PD/SCL and OE/SDA pins
is not available.
6.1 EEPROM Programming
Data must be loaded into the EEPROM in a most-
significant-bit (MSB) to least-significant-bit (LSB) order.
The register map of the EEPROM is noted in Table 3.
The device address of the EEPROM is:
A6
A5
A4
A3
A2
A1
A0
1
0
1
0
X
X
X
6.1.1 Write Operation
The EEPROM can only be written to with the Random
Register Write Procedure (see Page 8). The procedure
consists of the device address, the register address, a
R/W bit, and one byte of data.
Following the STOP condition, the EEPROM initiates its
internally timed 4ms write cycle, and commits the data
byte to memory. No acknowledge signals are generated
during the EEPROM internal write cycle.
If a stop bit is transmitted before the entire write com-
mand sequence is complete, then the command is
aborted and no data is written to memory.
If more than eight bits are transmitted before the stop bit
is sent, then the EEPROM will clear the previously loaded
data byte and will begin loading the data buffer again.
6.1.2 Acknowledge Polling
The EEPROM does not acknowledge while it internally
commits data to memory. This feature can be used to
increase data throughput by determining when the inter-
nal write cycle is complete.
The process is to initiate the Random Register Write Pro-
cedure with a START condition, the EEPROM device
address, and the write command bit (R/W=0). If the
EEPROM has completed its internal 4ms write cycle, the
EEPROM will acknowledge on the next clock, and the
write command can continue.
If the EEPROM has not completed the internal 4ms write
cycle, the Random Register Write Procedure must be
restarted by sending the START condition, device ad-
dress, and R/W bit. This sequence must be repeated until
the EEPROM acknowledges.
6.1.3 Read Operation
The EEPROM supports both the Random Register Read
Procedure and the Sequential Register Read Procedure
(both are outlined on Page 8).
5
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