AS6C3216A-55BIN View Datasheet(PDF) - Alliance Semiconductor

Part Name

Description

Manufacturer

AS6C3216A-55BIN

2048K x 16bit Low Power CMOS SRAM

Alliance Semiconductor 

WRITE CYCLE 3 (LB#,UB# Controlled) (1,4,5)

Address

CE#

CE2

LB#,UB#

tWC

tAW

tAS

tCW

tBW

WE#

Dout

tWP

tWHZ

(4)

Din

AS6C3216A-55BIN

tWR

High-Z

tDW

tDH

Data Valid

Notes :

1.A write occurs during the overlap of a low CE#, high CE2, low WE#, LB# or UB# = low.

2.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed

on the bus.

3.During this period, I/O pins are in the output state, and input signals must not be applied.

4.If the CE#, LB#, UB# low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a

high impedance state.

5.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.

Confidential

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Rev.1.0 June 2017

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