WM8199 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
WM8199 Datasheet PDF : 32 Pages
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WM8199
Production Data
ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD = DVDD1 = 5.0V, DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25°C, MCLK = 32MHz unless otherwise stated.
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
Overall System Specification (including 16-bit ADC, PGA, Offset and CDS functions)
Conversion rate
16
MSPS
Full-scale input voltage range
(see Note 1)
Max Gain
Min Gain
0.4
Vp-p
4.08
Vp-p
Input signal limits (see Note 2)
VIN
0
AVDD
V
Full-scale transition error
Gain = 0dB;
20
mV
PGA[7:0] = 4B(hex)
Zero-scale transition error
Gain = 0dB;
PGA[7:0] = 4B(hex)
20
mV
Differential non-linearity
DNL
1.25
LSB
Integral non-linearity
INL
36
LSB
Channel to channel gain matching
1
%
Total output noise
Min Gain
Max Gain
5
LSB rms
25
LSB rms
References
Upper reference voltage
VRT
2.85
V
Lower reference voltage
VRB
1.35
V
Input return bias voltage
VRX
1.65
V
Diff. reference voltage (VRT-VRB)
Output resistance VRT, VRB, VRX
VRTB
1.4
1.5
1.6
V
1.6
Ω
VRLC/Reset-Level Clamp (RLC)
RLC switching impedance
50
Ω
VRLC short-circuit current
2
mA
VRLC output resistance
2
Ω
VRLC Hi-Z leakage current
VRLC = 0 to AVDD
1
µA
RLCDAC resolution
4
bits
RLCDAC step size, RLCDAC = 0
RLCDAC step size, RLCDAC = 1
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 0
VRLCSTEP
VRLCSTEP
VRLCBOT
AVDD=5V
AVDD=5V
0.25
V/step
0.17
V/step
0.39
V
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 1
VRLCBOT
0.26
V
RLCDAC output voltage at
code F(hex) RLCDACRNG, = 0
VRLCTOP
AVDD=5V
4.14
V
RLCDAC output voltage at
code F(hex), RLCDACRNG = 1
VRLCTOP
2.81
V
VRLC deviation
25
mV
Offset DAC, Monotonicity Guaranteed
Resolution
8
bits
Differential non-linearity
DNL
0.1
0.5
LSB
Integral non-linearity
INL
0.25
1
LSB
Step size
2.02
mV/step
Output voltage
Code 00(hex)
-260
mV
Code FF(hex)
+260
mV
Notes:
1.
Full-scale input voltage denotes the peak input signal amplitude that can be gained to match the ADC full-scale
input range.
2.
Input signal limits are the limits within which the full-scale input voltage signal must lie.
w
PD, Rev 4.4, July 2008
6
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