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LC66PG5XX View Datasheet(PDF) - SANYO -> Panasonic

Part Name
Description
Manufacturer
LC66PG5XX Datasheet PDF : 14 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
LC66PG5XX
Continued from preceding page
Terminal
name
Input/
output
Function
PC0
PC1
PC2/VREF0
PC3/VREF1
I/O
Input/output port PC0 to PC3
•Data input and output in 4-bit units and in
1-bit units.
•PC2 also used as the VREF0 terminal for
reference voltage input.
•PC3 also used as the VREF1 terminal for
reference voltage input.
LC66PG5XX output
format
•Nch OD output
Option
(production chip)
•CMOS or Nch OD
output
At initial
reset
H
PD0/CMP0
I
Input port PD0 to PD3
PD1/CMP1
•Can be selected as comparator input
PD2/CMP2
terminals on programs.
PD3/CMP3
PD0 : reference voltage input (VREF0).
PD1 to PD3 : reference voltage input
(VREF1)
•PD0, PD1 (PD2 to PD3) selectable as
comparator input ports on programs in this
unit.
PE0/TRA
I
Input port
PE1/TRB
•Selectable as three-state input port on
programs.
Normal input
Normal input
OSC1
OSC2
I
Terminals for system clock oscillator
O
externally added.
•Leave OSC2 open and close OSC1 for
external clock signal input when external
clock mode is selected.
•Ceramic resonator
oscillation, RC (resistor
and capacitor) or
external clock selection.
RES
TEST
VDD
VSS
I
Terminal for system reset signal input.
•CPU to be initialized when P33/HOLD="H"
plus "L" level voltage is applied to the RES
terminal.
I
Terminal for CPU test signal input.
•Always connected to VSS during operation.
Power source terminal
No.2648–5/14

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