LC89057W-VF4A-E View Datasheet(PDF) - ON Semiconductor

Part Name

Description

Manufacturer

LC89057W-VF4A-E

Digital Audio Interface Transceiver

ON Semiconductor 

LC89057W-VF4A-E

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10.1.9 Output of Clock switch transition signal ( CKST )

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• CKST outputs "L" pulse when the output clock changes by PLL lock/unlock.

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• In the lock-in stage, the CKST "L" pulse falls at the word clock generated from the XIN clock after PLL is locked

following detection of input data, and rises at the same timing as RERR after a designated period.

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• In the unlock stage, the CKST "L" pulse falls at the same timing as RERR, PLL lock detection signal, and rises after

word clocks generated from the XIN clock are counted for a designated period.

• Change of the PLL lock status and timing of the clock change can be seen by detecting the rising and falling edges of

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the CKST "L" pulse.

RX0 to RX6

PLL status

XTAL clock

VCO clock

CKST

RERR

RMCK

UNLOCK

Digital data

LOCK

After PLL lock 45ms to 300ms

Same timing as RERR

(a): Lock-in stage

RX0 to RX6

PLL status

XTAL clock

VCO clock

CKST

RERR

RMCK

Digital data

UNLOCK

UNLOCK

Same timing as RERR 0.6ms to 6.4ms

(b): Unlock stage

Figure 10.4 Clock Switch Timing

No.7202-19/59

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