SMC032BFY6E View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
SMC032BFY6E
STMicroelectronics
SMC032BFY6E Datasheet PDF : 91 Pages
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Electrical interface
SMCxxxBF
Table 9. Signal Description (continued)
Signal Name
Dir.
Pin
READY
(PC Card Memory Mode)
O
37
–IREQ
(PC Card I/O Mode)
INTRQ
(True IDE Mode)
–REG
(PC Card Memory Mode)
–REG
(PC Card I/O Mode)
I
44
–DMACK
(True IDE Mode)
RESET
(PC Card Memory Mode)
RESET
I
(PC Card I/O Mode)
–RESET
(True IDE Mode)
VCC
(PC Card Memory Mode)
VCC
(PC Card I/O Mode)
VCC
(True IDE Mode)
41
13,38
Description
Indicates whether the Card is busy (Low), or ready to
accept a new data transfer operation (High). The Host
socket must provide a pull-up resistor. At power up and
Reset, the READY signal is held Low until the commands
are completed. No access should be made during this time.
The READY signal is held High whenever the Card has
been powered up with RESET continuously disconnected or
asserted.
Interrupt Request. It is strobed Low to generate a pulse
mode interrupt or held Low for a level mode interrupt.
Active High Interrupt Request to the host.
Used to distinguish between Common Memory and
Register (Attribute) Memory accesses. High for Common
Memory, Low for Attribute Memory.
Must be Low during I/O Cycles when the I/O address is on
the Bus.
The –DMACK input signal is used to acknowledge DMA
transfers. It is asserted by the host in response to DMARQ
to initiate the transfer.
When DMA mode is disabled, the Card should ignore the
-DMACK signal.
If the host does not support DMA mode, but only True IDE
mode, this signal should be driven High or tied to VCC by the
host.
Resets the Card (active High). The Card is Reset at power
up only if this pin is left High or unconnected.
Same as PC Card Memory Mode.
Hardware Reset from the host (active Low).
+5V, +3.3V power.
Same for all modes.
Same for all modes.
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