MSP3400CPP View Datasheet(PDF) - Micronas

Part Name

Description

Manufacturer

MSP3400CPP

Multistandard Sound Processor

Micronas 

PRELIMINARY DATA SHEET

MSP 3400C

4. Architecture of the MSP 3400C

Fig. 4–1 shows a simplified block diagram of the IC. Its

architecture is split into three functional blocks:

1. demodulator section

2. digital signal processing (DSP) section performing

audio baseband processing

3. analog section containing two A/D-converters,

6 D/A-converters, and SCART switching facilities

4.1. Demodulator Block

4.1.1. Analog Sound IF – Input Section

The input pins ANA_IN1+, ANA_IN2+, and ANA_IN–

offer the possibility to connect two different sound IF

sources to the MSP 3400C. By means of bit [8] of

AD_CV (see Table 6–3), either terrestrial or satellite

sound IF signals can be selected. The analog-to-digital

conversion of the preselected sound IF signal is done by

a flash-converter, whose output can be used to control

an automatic gain circuit (AGC), providing optimum level

for a wide range of input levels. It is possible to switch

between automatic gain control and a fixed (setable) in-

put gain. In the optimum case, the input range of the A/D

converter is completely covered by the sound IF source.

Some combinations of SAW filters and sound IF mixer

ICs, however, show large picture components on their

outputs. In this case, filtering is recommended. It was

found that the high pass filters formed by the coupling

capacitors at pins ANA_IN1+ and ANA_IN2+ as shown

in the application diagram are sufficient in most cases.

4.1.2. Quadrature Mixers

The digital input coming from the integrated A/D conver-

ter may contain audio information at a frequency range

of theoretically 0 to 9 MHz corresponding to the selected

standards. By means of two programmable quadrature

mixers two different audio sources, for example FM1

and FM2, may be shifted into baseband position. In the

following, the two main channels are provided to pro-

cess either:

– FM mono (channel 2) or

– FM2 (channel 1) and FM1 (channel 2).

Two independent digital oscillators are provided to gen-

erate two pairs of sin/cos-functions. Two programmable

increments, to be divided up into Low- and High Part, de-

termine frequency of the oscillator, which corresponds

to the frequency of the desired audio carrier. In section

6.1., format and values of the increments are listed.

S_CL / ADR_CL

S_DA_IN / ADR_DA S_ID / ADR_WS

SBUS/ADR Interface

I2S_DA_OUT

I2S_CL AUD_CL_OUT XTAL_OUT

I2S_DA_IN_1/2 I2S_WS

XTAL_IN

I2S Interface

Audio PLL

Sound IF

ANA_IN1+

ANA_IN2+

Mono

MONO_IN

SC1_IN_L

SCART1

SC1_IN_R

SC2_IN_L

SCART2

SC2_IN_R

SC3_IN_L

SCART3

SC3_IN_R

Demodulator

A/D

A/D

S1..4

I2S1/2L/R I2SL/R

FM1 / AM

FM2

LOUD-

SPEAKER L

LOUD-

SPEAKER R

DFP

IDENT

HEADPHONE L

HEADPHONE R

SCART_L

SCART_R

SCART_L

SCART_R

D/A

D/A

D/A

D/A

D/A

D/A

SCART Switching Facilities

Fig. 4–1: Architecture of the MSP 3400C

Micronas

DACM_L

Loudspeaker

DACM_R

DACA_L

Headphone

DACA_R

SC1_OUT_L

SCART 1

SC1_OUT_R

SC2_OUT_L

SCART 2

SC2_OUT_R

9

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