ICS601-02 View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

Manufacturer

ICS601-02

LOW PHASE NOISE CLOCK MULTIPLIER

Integrated Device Technology 

LOW PHASE NOISE CLOCK MULTIPLIER

DATASHEET

ICS601-02

Description

The ICS601-02 is a low cost, low phase noise, high

performance clock synthesizer for any application that

requires low phase noise and low jitter. The ICS601 is IDT’s

lowest phase noise multiplier. Using IDT’s patented analog

and digital Phase Locked Loop (PLL) techniques, the chip

accepts a 10–27 MHz crystal or clock input, and produces

output clocks up to 170 MHz at 3.3 V. A separate supply pin

is provided so that the output can be 2.5 V.

This product is intended for clock generation. It has low

output jitter (variation in the output period), but input to

output skew and jitter are not defined nor guaranteed. For

applications which require defined input to output timing,

use the ICS670-01.

Features

• Packaged in 16-pin SOIC (Pb free)

• Uses fundamental 10 - 27 MHz crystal or clock

• Patented PLL with the lowest phase noise

• Output clocks up to 170 MHz at 3.3 V

• Output Enable function tri-states outptus

• Low phase noise: -132 dBc/Hz at 10 kHz

• Low jitter - 18 ps one sigma

• Full swing CMOS outputs with 25 mA drive capability at

TTL levels

• Advanced, low power, sub-micron CMOS process

• Industrial temperature range (-40 to +85°C)

• 3.3 V or 5 V core VDD. Output clock can operate down to

2.5 V

Block Diagram

VDD

VDDP

Reference

Divider

Phase

Comparator

Charge

Pump

Loop

Filter

VCO

CLK

X1/ICLK

Crystal or

clock input

X2

Optional crystal

capacitors needed

for accurate tuning

(not shown)

Crystal

Oscillator

ROM Based

Multipliers

VCO

Divide

4

S3:0

GND

OE

IDT™ LOW PHASE NOISE CLOCK MULTIPLIER

1

ICS601-02

REV G 051310

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