DS2153Q View Datasheet(PDF) - Maxim Integrated

Part Name

Description

Manufacturer

DS2153Q

E1 Single-Chip Transceiver

Maxim Integrated 

DS2153Q

3 PARALLEL PORT

The DS2153Q is controlled via a multiplexed bidirectional address/data bus by an external

microcontroller or microprocessor. The DS2153Q can operate with either Intel or Motorola bus timing

configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will

be selected. All Motorola bus signals are listed in parentheses (). See the timing diagrams in Section 14

for more details. The multiplexed bus on the DS2153Q saves pins because the address information and

data information share the same signal paths. The addresses are presented to the pins in the first portion of

the bus cycle and data will be transferred on the pins during second portion of the bus cycle. Addresses

must be valid prior to the falling edge of ALE (AS), at which time the DS2153Q latches the address from

the AD0 to AD7 pins. Valid write data must be present and held stable during the later portion of the DS

or WR pulses. In a read cycle, the DS2153Q outputs a byte of data during the latter portion of the DS or

RD pulses. The read cycle is terminated and the bus returns to a high-impedance state as RD transitions

high in Intel timing or as DS transitions low in Motorola timing.

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